Yes, a Link Width of 32 lanes was legal / supported ... in PCI Express versions 1.0 through 5.0. It has not been often used by hardware vendors.
Another thing to consider is that when devices are using an active link width this wide, it suggests that processor core access to other Memory, data fabric, etc. would be similarly upsized - if the whole system is expected to leverage that greater I/O or accelerator capacity.
Starting in PCI Express 6.0 a link width of 32 lanes is no longer supported, or defined as valid by the PCI-SIG Base protocol Specification. x16 Link Width is the greatest defined link width to be supported by a PCIe 6.x component.
