The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of ZVS Synchronous Buck Converter

ACEEE Int. J. on Control System and Instrumentation, Vol. 02, No. 02, June 2011

The Analysis of Dead Time on Switching Loss in High
and Low Side MOSFETs of ZVS Synchronous Buck
Converter
N.Z. Yahaya, M.K. Lee, K.M. Begam & M. Awan
Power & Energy Group
Electrical Engineering Department
Universiti Teknologi PETRONAS
Bandar Seri Iskandar, Tronoh, 31750 Perak, MALAYSIA
Email: norzaihar_yahaya@petronas.com.my

Abstract—This work is about the analysis of dead time variation D, dead time, TD, and the resonant inductor, Lr are the limiting
on switching losses in a Zero Voltage Switching (ZVS) parameters that influence the gate driver operation from
synchronous buck converter (SBC) circuit. In high frequency conducting optimally. These parameters had been analyzed in
converter circuits, switching losses are commonly linked with [6] and the results show that the optimized values are found to
high and low side switches of SBC circuit. They are activated
be D = 20 %, TD = 15 ns and Lr = 9 nH at 1 MHz switching
externally by the gate driver circuit. The duty ratio, dead time
and resonant inductor are the parameters that affect the
frequency. However, the values of switching losses in the
efficiency of the circuit. These variables can be adjusted for MOSFET are still very high. Therefore, the TD parameter is
the optimization purposes. The study primarily focuses on adjusted to optimize switching losses. This is the primary
varying the settings of input pulses of the MOSFETs in the objective in this work.
resonant gate driver circuit which consequently affects the
performance of the ZVS synchronous buck converter circuit. II. PROPOSED RGD-SBC CIRCUIT
Using the predetermined inductor of 9 nH, the frequency is
maintained at 1 MHz for each cycle transition. The switching
loss graph is obtained and switching losses for both S 1 and S2
are calculated and compared to the findings from previous
work. It has shown a decrease in losses by 13.8 % in S1. A dead
time of 15 ns has been determined to be optimized value in
the SBC design.

Keywords— PSpice Simulation, Resonant Gate Driver,
Synchronous Buck Converter, Switching Losses

I. INTRODUCTION
In megahertz switching frequency, synchronous buck
converter (SBC) circuit may contain losses which are normally
caused by the high and low side switches. The resonant gate
driver (RGD) circuit is applied due to its suitability in driving
MOS-gated power switches in high frequency applications. High
power Metal Oxide Semiconductor Field Effect Transistor Figure 1. Proposed RGD Circuit
(MOSFET) is used as a switch in this work of the proposed RGD
Fig. 1 shows the proposed RGD circuit which is used in this
circuit [1]. At present, there are various types of RGD circuits
work. The circuit is suitable for SBC circuit because with a single
commercially available [2-4]. The resonant circuit transfers energy
input voltage, Vin, two output gate voltages will be generated
from the parasitic input capacitance of the power switching
complimentarily. Fig. 2 shows two output waveforms generated
devices. This energy transfer prevents dissipation of the
from an input voltage of the SBC circuit.
capacitive energy in the driver circuit which may otherwise
As it can be seen, the left circuit of the proposed RGD
destroy one or more components. The resonant circuit includes
circuit is the DC-RGD while the right circuit is just the sym-
an inductor in the driver circuit and one or more discrete
metrical of the left circuit. The circuit has the advantages
capacitors are also included within the driver circuit to maintain
with simplicity having symmetrical pattern which gives bet-
resonance at a given frequency regardless of parasitic
ter choice of component and parameter modification. In addi-
capacitance variation [5]. Although high frequency MOSFET
tion, a bootstrap circuit for high side driver [3] consisting of
is used, yet there are limitations in the design. When the
a diode, Da and a capacitor, Ca are added into the circuit.
frequency is increased, the gate driving losses will experience
The importance of bootstrap circuitry is that it aids in circuit
an increase in power dissipation. This in turn affects the
simplification, symmetrical behavior and also minimizes
performance of the converter. The duty ratio or pulse width,
switching loss.
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When the values of switching frequency equals to 1 MHz and
Lr = 9 nH, together with the optimized value of TD are unchanged,
any changes in D will eventually result in different switching
losses in the circuit.

III. METHODOLOGY
In this work, the proposed RGD-SBC circuit is simulated
using PSpice software. The pulse settings of four MOSFETs in
the proposed RGD circuit are modified carefully resulting in
different values of TD. The RGD circuit accordingly will affect
the TD of the synchronous buck converter circuit where the
switching losses of the circuit are measured at the two MOSFET
switches of S1 and S2. The results are then measured, compared
and analyzed. The conclusion is then drawn.

IV. RESULTS AND DISCUSSION
Figure 2. Gate Voltage of S 1 and S2 & Input Voltage of SBC A. Proposed RGD Circuit
Besides that, it has less impact on the parasitic capacitance The dead time settings on each pulse generator in the
as well as better immunity in dv/dt turn-on. The proposed RGD proposed RGD circuit of Fig. 1 are shown in Table I while the
circuit can conduct in two modes, complementary mode and pulse width settings are tabulated in Table II. Fig. 4 to Fig. 6
symmetrical mode. In the complementary mode, it provides two indicate the waveforms of dead time, delay time and pulse width.
drive signals with duty cycle D and 1-D, respectively. This mode
is suitable for driving two MOSFETs in a synchronous buck TABLE I
SETTINGS FOR DEAD TIME IN PROPOSED RGD CIRCUIT
converter. In the circuit, the four units of MOSFETs (Q1, Q2,
Q3, Q4) settings will be reassigned carefully while other values
which include oscillation frequency = 1 MHz, D = 20 % and Lr
= 9 nH remain unchanged. Theoretically, when parameters of
MOSFETS, Q1 and Q2 of the RGD circuit are changed, dead
time of the left circuit, TD1 will vary. Similarly, when parameter
values of Q3 and Q4 are changed, then dead time of the right
circuit, TD2 will be also be modified. Consequently, the overall
value of TD in the proposed synchronous buck converter
circuit as shown in Fig. 3 will also be modified. This gives TABLE II
result in new values of D and (1-D) in the synchronous buck SETTINGS FOR PULSE WIDTH IN PROPOSED RGD CIRCUIT
circuit. S1 is the high side switch while S2 is the lower side
switch and the switching losses of the circuit will be measured
from these two switches. Overall, it is expected that the by
varying the value of TD, the performance of the SBC circuit
will be affected, accordingly.

The dead times are varied in order to evaluate the performance
of the circuit. For different dead times, the initial delay time,
td,initial is set to be constant at 15 ns. Therefore, the first delay time
for voltage pulse one, td1 is equal to td,initial. By taking TD=15 ns as
reference, it can be observed that only delay time for voltage
pulse 1 and 3, td1 and td3 , and pulse width of voltage pulse of 1
and 3, PW1 and PW3, are changed in order to obtain the dead
times of 5 ns and 30 ns. The table also shows that when TD1=TD2
increases, TD3 decreases instead.
The graph of Fig. 4 is generated from the simulation of Vgs,Q1
and Vgs,Q2. Both Q1 and Q2 MOSFETs conduct complementarily
to each other. The time when both MOSFETs are not conducting
is known as the dead time, TD1. Vp1 is the pulse width of Q1 and
Figure 3. Proposed Synchronous Buck Converter with ZVS similarly to Vp2, the pulse width of Q2. td, initial which is equal to td1
is the initial delay time, set at a constant value of 15 ns. td2 on the
other hand is the delay time before Q2 starts to conduct.
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pulse width PWS2. TD3 is the dead time when both switches are
not conducting. Fig. 7 shows the operating waveforms generated
from the left side of the proposed RGD circuit in Fig. 1.

Figure 4. Indication of Pulse Width, Dead Time and Delay Time of
Q1 and Q2 MOSFETs for TD=15 ns

Figure 7. Operating Waveforms of Proposed RGD Circuit
Pulses from Vp1 and Vp2 are fed into the MOSFETS, Q1 and
Q2 on the left side of RGD circuit. From the waveform, Q1 and Q2
are complementary driving pair inherited from the conventional
driver. First, when Q1 is switched on, the inductor current of the
left circuit, iL1 starts to conduct and it is charged to maximum.
The characteristic impedance of the resonant circuit can be
represented by (1)

(1)

Figure 5. Indication of Pulse Width, Dead Time and Delay Time of where LR is the resonant inductor equivalent to 9 nH. The rise
Q3 and Q4 MOSFETs for TD=15 ns time tr can be estimated by (2)
Fig. 5 shows the pulse width for Q3, Vp3 and Q4, Vp4. td3 is
the delay time before the MOSFET Q3 starts to conduct. Similarly, (2)
td4 is the delay time before Q4 turns on. On the other hand, TD2 is
the dead time when both MOSFETs, Q3 and Q4 are off. The duration of this charging current depends on the value
of LR for being the time constant of the circuit. If the duration of
the discharging current is not sufficient, it will cause current
oscillation when Q1 is turned off [1]. On the other hand, D1 and
D2 are designed to clamp Vgs and to provide low impedance path
for the inductor current and recover the driving energy which is
represented by (3)

(3)
where Cin is the input gate capacitance of high side switch, S1.
On the other hand, the peak time is defined by (4)

Figure 6. Indication of Pulse Width and Delay Time for S 1 and S2 for
TD=15 ns (4)
The gate source voltage of both switches, Vgs,S1 and Vgs,S2 is
shown in Fig. 6. The maximum of Vgs,S1 is at 10 V and PWS1 is the
pulse width of S1. Vgs,S2 goes to a maximum value of 12 V with
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TABLE III
After iL1 has been fully charged to peak current and at the same SWITCHING LOSS FOR VARYING DUTY RATIO OF S2 AT TD=15 NS
moment Vgs,S1 is clamped at Vca by diode D1, iL1 flows according
to the path Q1-L1-Vgs,S1. The inductor current can be represented
by equation (5).

iL1 then starts to discharge back to zero through Q2,body diode,-L1- From the results, the duty ratio of S2 at 75 % gives the lowest
D1 and back to Vca, the direct voltage source at 12 V. After a switching losses compared to other values. Therefore, it can be
predetermined TD of either 5 ns, 10 ns or 15 ns, Q2 will turn on concluded that in order to reduce the conduction losses in the
instead. At this time Q1 is turned off. Then iL1 starts to charge circuit, the conduction time of S2 has to be optimized at 75 % for
again but to a negative maximum value. This value will be a little low switching loss. These two switches conduct
lower compared to the positive value of iL1 because of leakage complementary to each other. Since both of them do not turn
current. iL1 shows a symmetrical behavior compared to when Q1 on at the same time, cross conduction will not occur. During
is conducting. When iL1 increases back to zero, it goes through TD, when S1 is turned off, the discharged inductor current at
D2-L1,-Q1,body diode and to Vca. The symmetrical behavior in the load will flow into body diode S2, which is also at its off
charging and discharging inductor current gives the total RG condition. ZVS can be achieved if S2 is completely turned off
power loss to be (6). before S1 is turned on. During the Discontinuous Current
Mode (DCM) operation, the negative load inductor current
can be applied where the body diode of S1 is turned on first
before the main body of the switch itself. Therefore, the
switching losses at S1 can be reduced since it has experienced
The t1 represents the rise time of the inductor current while t2
ZVS. The operating waveforms of the proposed SBC circuit
is the recovery time of the inductor current. The same operation
in simulation are shown in Fig. 8.
applies for the right hand side of the proposed RGD circuit in
Fig. 1 with TD2 = 5 ns, 15 ns or 30 ns. The circuit can also be
explained in terms of energy processing. When Q1 is turned on,
energy is transferred from the power source, Vca to the resonant
inductor and the gate capacitor. When Vgs of Q1 reaches its
peak, freewheeling of energy at inductor occurs. Then, the energy
is returned to Vca. Therefore, the proposed RGD demonstrates
less power consumption compared to the conventional gate
driver because of the energy recovery process. The circuit also
has the similar circuit operation for the discharging transition.
When Q2 is turned on, resonance takes place and the capacitive
energy is transferred to the inductor. When iL1 starts to increase
to the negative peak value, energy is merely freewheeling and
finally, when the inductor current returns to zero, the inductor
energy is also returned to the power source, Vca. The right circuit
operates in similar fashion to the left circuit but during different
interval.
A. Proposed SBC Circuit
Referring to Fig. 3, S1 is the high side switch and it has the
primary function of a buck converter, used to convert high input
voltage into low output voltage at the load. On the other hand,
S2 is the low side switch and it has a longer conduction time
compared to S1. The purpose is to lower the conduction loss in
Figure 8. Operating Waveforms of SBC Circuit
S2. This can be verified by Table III.
From the results, the duty ratio of S2 at 75 % gives the lowest From the waveforms, the operation of SBC circuit starts when
switching losses compared to other values. Therefore, it can be S1 starts to conduct while ids,S2 at its peak value starts to decrease
concluded that in order to reduce the conduction losses in the to zero and turn off. At this time, it can be seen that Vds, S2 starts
circuit, the conduction time of S2 has to be optimized at 75 % for to increase to its maximum value which is the Vin value of 48 V
low switching loss. while Vds, S1 works in complimentary pattern and reduces to zero.
The scenario of Vds, S2 going to its peak value while Vds, S1 goes to
zero should occur at the same time, in other words, there is no
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time interval. This is because of freewheeling phase of ids, S1. It off or near to zero value during the entire turn-off transition time.
causes Vgs, S1 to go to zero first before Vds, S1 reaches its maximum Similarly to Vds,S2, having a zero drain voltage can result in zero
value. For the drain current of S1, it can be observed that ids, S1 switching loss since their drain currents conduct at this time.
starts to increase exponentially to its highest value. At this This situation can be seen in the Fig. 10.
moment, the conduction of ids, S1 circulates through Ls and Cs in
the SBC circuit. S1 stops conducting when it reaches its highest
point. But at this moment, S2 does not conduct yet. This indicates
a dead time exists when there is a change in conduction of
switches. At this time, Vds, S1 starts to increase while Vds, S2 starts
to decrease. On the other hand, ids, S2 starts to decrease to its
maximum negative value whereas ids, S1 is at zero. Following that,
it can be seen from the figure ids, S2 starts to increase back to zero,
which is like the previous state before it increases to its highest
value while S1 is off. At this moment, it can be observed that ids,
S1
is at zero and Vds, S1 is at its peak of the value Vin. This process
repeats in the next subsequent cycles.
C. Switching Losses of SBC at TD = 15 ns
The power losses of the circuit are interpreted by
generating the turn-off switching loss waveform of S1 and
Figure 10. Floating Point of Vds,S1
turn-on switching loss of S2 as shown in Fig. 9
It can also be observed that the positive peak is higher
than the negative. This shows that the power losses are not
equally distributed in S1. In the circuit, S1 is dominant in
generating the power loss of the SBC circuit. Thus, Ls and Cs
has been added to the circuit in parallel with S1 to solve this
problem. Meanwhile, Cx has also been added in order to
prevent the floating drain voltage of S1. Hence, theoretically,
Ls, Cs and Cx have to be varied to reduce the switching losses
at S1. However, S2 turn-on switching losses have increased
by 15.12 % compared to the study in [1]. Fig. 11 shows the
operating waveforms for S2.

Figure 9. Turn-Off Switching Loss of S 1 and Turn-On Switching Loss
of S 2
From the waveforms, the switching time for S1 turn-off
transition is 35 ns and for S2, 40 ns. The calculation of switching
losses is tabulated in Table IV and the evaluated results are
compared with [1].
TABLE IV
COMPARISON OF DATA [1] WITH THIS WORK AT TD=15NS

Figure 11. Operating Waveforms of S 2
Compared to S1, there is no floating point at Vds, S2. As
expected there is reduction in the turn-on switching losses and
in return, the performance and reliability of the SBC circuit have
improved.
From the results, it can be observed that the turn-off switching D. Comparison of Circuit Performance for Several TDs
losses of S1 have decreased. Otherwise, the problem of floating
With other parameter values remain unchanged except for
Vds,S1 can cause the switching power loss to float as well.
TD, the overall performance of the circuit is analyzed. The circuit
Conventionally, as most described in literature, the switching
performance at TD =5 ns, 15 ns, and 30 ns is shown in Table V
losses will be high and unfortunately they are ignored. The aim
and Table VI.
is to generate the drain voltage of less than 0.7 V during its turn-
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TABLE V The difference between the results obtained from PSpice done
PARAMETER EVALUATION FOR VARYING TD S in this work and [1] show significant big margin. The work done
in [1] shows lower PBD since the proposed RGD design in Fig. 1
gives result in low body diode conduction time during TD of 15
ns. This corresponds to the conduction loss of the switching
MOSFETs as well. Other than these, the simulation results are
acceptable. Nevertheless this work has successfully verified
that 15 ns dead time is the best value to be used for the lowest
TABLE VI switching loss in the converter.
POWER LOSSES FOR VARYING TDS
V. CONCLUSION
In conclusion, switching losses in converter circuit are
present due to high and low side switches operating in high
frequency system. The gate driver circuit plays an important
part in activating these switches. In order to reduce the losses,
the dead time and duty ratio of the RGD circuit must be
Ploss,total is the total of all losses consisting conduction loss, controlled. The PSpice software is used to implement this
PCOND , body diode loss, PBD , and also switching losses, project. The switching losses for both S1 and S2 are calculated
PSW,S1 and PSW,S2 . From Table VII, it indicates that TD at 15 ns and compared to the findings from [1]. It has shown a decrease
gives the lowest total power loss, Ploss,total of 2.296 W. Com- in losses by 13.8 % in S1 but increase by 15.12 % in S2,
pared to TD=5 ns and TD=30 ns, TD=15 ns is the most energy respectively. Moreover, further analyses and comparison of
saving setting to be used. The switching losses, PSW of the the circuit performance are also made and it can be concluded
circuit are the major contributors of losses. PSW comes from that TD =15 ns is the best optimum value.
the two switches, S1 and S2, in the synchronous buck con-
verter circuit. Theoretically, these losses can be reduced by ACKNOWLEDGMENT
reducing the switching time or peak power of both switches
Authors would like to thank Universiti Teknologi
since PSW =0.5*switching time*peak power*fs. This means
PETRONAS, for providing financial support in presenting this
that the faster the MOSFETs can turn off, the more switching
work.
power can be reduced.
E. Results Verifications REFERENCES
Utilizing Mathcad, equations (2), (3) and (4) are used to obtain [1] N.Z. Yahaya, K.M. Begam & M. Awan “Design & Simulation
the theoretical values. The results are then compared with the of An Effective Gate Drive Scheme for Soft-Switched
values obtained using Pspice. All parameters are calculated and Synchronous Buck Converter” 3 rd Asia International
the comparison is shown in Table VII. Conference on Modeling & Simulation, Bandung/Bali,
Indonesia, pp. 751-756, May 2009.
TABLE VII [2] K. Yao and F.C. Lee “A Novel Resonant Gate Driver for High
C OMPARISON OF CALCULATION FROM MATHCAD & PSPICE AT TD =15 NS
Frequency Synchronous Buck Converters” IEEE Transactions
on Power Electronics, vol. 17, no. 2, pp. 180-186, Mar. 2002.
[3] Z. Yang, S. Ye and Y. Liu “A New Resonant Gate Driver
Circuit for Synchronous Buck Converter” IEEE Transactions
on Power Electronics, vol. 22, pp 1311-1320, Jul. 2007.
[4] Y.H. Chen, F.C. Lee, L. Amoroso and H. Wu “A Resonant
MOSFET Gate Driver with Energy Efficient Recovery” IEEE
Transactions on Power Electronics, vol. 19, no. 2, Mar. 2004.
[5] J. Qian “High Efficiency High Frequency Resonant Gate Driver
for Power Converter”, Aug. 2002,
www.freepatentsonline.com/6441652.html
[6] N.Z. Yahaya, K.M. Begam & M. Awan “The Limitations and
Implications on Duty Ratio, Dead Time and Resonant Inductor
on DC-RGD Circuit” 2nd National Postgraduate Conference
on Engineering, Science and Technology, Tronoh, Malaysia,
Mar 2009, unpublished.

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The Analysis of Dead Time on Switching Loss in High and Low Side MOSFETs of ZVS Synchronous Buck Converter

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