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Vinay Patil

This document provides a summary of Vinay Kumar's professional experience and qualifications. He has over 3 years of experience in IP and SoC level verification using SystemVerilog, Verilog, and VHDL. Some of his skills and experience include UVM methodology, protocols like UART, I2C, AMBA, and Ethernet, debugging RTL and test benches, and developing verification environments. He has worked on projects involving an Ethernet load balancer FPGA, an AMBA AHB verification IP, and a NAND flash controller. Vinay holds a BE in electronics from SLN College of Engineering and a post-graduate diploma in VLSI from C-DAC.

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VINAY KUMAR Mobile No: +91 9880599255 Email id: vinaypatileklas@gmail.com PROFESSIONAL EXPERIENCE SUMMARY • 3years 6monthd of experience in IP and SoC level verification. • Proficiency in System Verilog, Verilog and VHDL languages. • Experience in Verification Environment, Test cases, Test Benches, Regression, Coverage, RTL Verification, Methodology – UVM • Protocols: UART, I2C , AMBA – AHB and Ethernet. • Worked on NAND Flash Controller. • Worked on coding of driver, monitor, protocol checkers, DPI-C and RAL. • Worked on debugging RTL, Design Document and RTL Development. • Created test benches in SV. WORK EXPERIENCE VVDN Technologies Ltd(current) IP Verification Engineer, since January 2014. NEC Technologies India Limited Member Technical Staff, Verification Team, from March 2012 to January 2014. TECHNICAL SKILLS Domain : Design & Verification. HDL : Verilog and VHDL HVL : SystemVerilog Methodology : UVM Languages : Basics of C and C++ Protocols/Interfaces : AMBA( AHB), Ethernet protocol, UART, BT.656, RFBI. EDA Tools : Mentor (Modelsim), Synopsys (VCS), Xilinx, Quartus II Specialties : Good Understanding of design & Verification flow. Application Skills : MS Office, VI editors PROJECTS: 1. CTBFPGA: It is a load balancer FPGA operating between L2 and PHY layer of the networking protocol. The FPGA aims at fragmentation of Ethernet packets and reassembly. It operates in 3 different modes to avoid traffic congestion and data corruption. Role : • Testcase identification and development for all the functional scenarios. • Took part in development of Verification plan document and test environment. • Debugging the RTL and Board testing, Register Set verification.
• Golden Reference Model development in C and interfacing it with SytemVerilog environment through Direct Programming interface (DPI-C). 2. Development of AMBA AHB Verification IP: Verification IP has been developed for AMBA AHB-Lite master using System Verilog, UVM Methodology. Tool used: Modelsim SE-64 10.2c Role: • Understanding AMBA AHB Protocol, Test case Identification, Verification Plan Document preparation. • Development of UVM Verification environment and sequences to cover various possible scenarios of AHB. • SV Assertions to check protocol compliance and Cover Groups created for functional coverage. 3. Design and Verification Hardley Davidson’s Skully Helmet Project: Description: Implemented FPGA design for routing and of standard BT.656 image from imager/Overlayed image stream from Media processor to the display controller. Role: • FPGA design document implementation. • RTL designing and synthesis on Lattice Machxo2 FPGA, using Lattice Diamond tool. • Video detect block, BT.656 test pattern generator block design. • Development of verification plan document, test plan document. • Verification environment is setup in system Verilog using UVM methodology. Tool used in Modelsim 10.2c version. 3. Nand Flash Controller for Freescale’s iNIC Card(FSLU_NVMe): Development of NAND Flash storage card. Role: • Development of System verilog Test Enviornment. • Development of verification plan document, test plan document. • Development of NAND Flash controller Test environment. • Integration of Nand flash controller with software interface(PCIe endpoint). • Hard IP of Altera StratixV FPGA is being used to latch commands from host pc. • Tool used in Modelsim 10.2c version. EDUCATIONAL QUALIFICATION: Coarse Institution Year of passing Passing grade SSLC Tagore Memorial Boy’s High School Raichur 2004-05 90.08% PUC Sadvidya Compisite PU college Mysore 2007-08 83.67% BE SLN College Of Engineering Raichur 2010-11 70%
PG-DIPLOMA (VLSI) Advanced Computing Training school, C- DAC, Pune 2011-12 60% EXTRA CURRICULAR ACTIVITIES AND ACHIEVEMENTS • Worked as team leader to organize various activities in college. • Participated in various quizzes and won prizes at district level. • Company representative for Cultural Sensitization activities between Indian and Japanese employees. • Actively participated with Japanese counterpart to synchronize the project practices between India and Japan. PERSONAL DETAILS: FATHER’S NAME : Mr. Doddan Gowda MOTHER’S NAME : Mrs. Parvathi DATE OF BIRTH : 12/08/1989 HOBBIES : Listening music LANGUAGES KNOWN : Kannada, Telugu, Hindi and English. PERMANENT ADDRESS : Eklaspur, Raichur, Karnataka- 584103 (Vinay Kumar) 1th Oct 2015

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Resume

  • 1. VINAY KUMAR Mobile No: +91 9880599255 Email id: vinaypatileklas@gmail.com PROFESSIONAL EXPERIENCE SUMMARY • 3years 6monthd of experience in IP and SoC level verification. • Proficiency in System Verilog, Verilog and VHDL languages. • Experience in Verification Environment, Test cases, Test Benches, Regression, Coverage, RTL Verification, Methodology – UVM • Protocols: UART, I2C , AMBA – AHB and Ethernet. • Worked on NAND Flash Controller. • Worked on coding of driver, monitor, protocol checkers, DPI-C and RAL. • Worked on debugging RTL, Design Document and RTL Development. • Created test benches in SV. WORK EXPERIENCE VVDN Technologies Ltd(current) IP Verification Engineer, since January 2014. NEC Technologies India Limited Member Technical Staff, Verification Team, from March 2012 to January 2014. TECHNICAL SKILLS Domain : Design & Verification. HDL : Verilog and VHDL HVL : SystemVerilog Methodology : UVM Languages : Basics of C and C++ Protocols/Interfaces : AMBA( AHB), Ethernet protocol, UART, BT.656, RFBI. EDA Tools : Mentor (Modelsim), Synopsys (VCS), Xilinx, Quartus II Specialties : Good Understanding of design & Verification flow. Application Skills : MS Office, VI editors PROJECTS: 1. CTBFPGA: It is a load balancer FPGA operating between L2 and PHY layer of the networking protocol. The FPGA aims at fragmentation of Ethernet packets and reassembly. It operates in 3 different modes to avoid traffic congestion and data corruption. Role : • Testcase identification and development for all the functional scenarios. • Took part in development of Verification plan document and test environment. • Debugging the RTL and Board testing, Register Set verification.
  • 2. • Golden Reference Model development in C and interfacing it with SytemVerilog environment through Direct Programming interface (DPI-C). 2. Development of AMBA AHB Verification IP: Verification IP has been developed for AMBA AHB-Lite master using System Verilog, UVM Methodology. Tool used: Modelsim SE-64 10.2c Role: • Understanding AMBA AHB Protocol, Test case Identification, Verification Plan Document preparation. • Development of UVM Verification environment and sequences to cover various possible scenarios of AHB. • SV Assertions to check protocol compliance and Cover Groups created for functional coverage. 3. Design and Verification Hardley Davidson’s Skully Helmet Project: Description: Implemented FPGA design for routing and of standard BT.656 image from imager/Overlayed image stream from Media processor to the display controller. Role: • FPGA design document implementation. • RTL designing and synthesis on Lattice Machxo2 FPGA, using Lattice Diamond tool. • Video detect block, BT.656 test pattern generator block design. • Development of verification plan document, test plan document. • Verification environment is setup in system Verilog using UVM methodology. Tool used in Modelsim 10.2c version. 3. Nand Flash Controller for Freescale’s iNIC Card(FSLU_NVMe): Development of NAND Flash storage card. Role: • Development of System verilog Test Enviornment. • Development of verification plan document, test plan document. • Development of NAND Flash controller Test environment. • Integration of Nand flash controller with software interface(PCIe endpoint). • Hard IP of Altera StratixV FPGA is being used to latch commands from host pc. • Tool used in Modelsim 10.2c version. EDUCATIONAL QUALIFICATION: Coarse Institution Year of passing Passing grade SSLC Tagore Memorial Boy’s High School Raichur 2004-05 90.08% PUC Sadvidya Compisite PU college Mysore 2007-08 83.67% BE SLN College Of Engineering Raichur 2010-11 70%
  • 3. PG-DIPLOMA (VLSI) Advanced Computing Training school, C- DAC, Pune 2011-12 60% EXTRA CURRICULAR ACTIVITIES AND ACHIEVEMENTS • Worked as team leader to organize various activities in college. • Participated in various quizzes and won prizes at district level. • Company representative for Cultural Sensitization activities between Indian and Japanese employees. • Actively participated with Japanese counterpart to synchronize the project practices between India and Japan. PERSONAL DETAILS: FATHER’S NAME : Mr. Doddan Gowda MOTHER’S NAME : Mrs. Parvathi DATE OF BIRTH : 12/08/1989 HOBBIES : Listening music LANGUAGES KNOWN : Kannada, Telugu, Hindi and English. PERMANENT ADDRESS : Eklaspur, Raichur, Karnataka- 584103 (Vinay Kumar) 1th Oct 2015