Publications and Honors (Ming-Long Fan)

Ming-Long Fan
Journal:
(1) Vita Pi-Ho Hu, Yu-Sheng Wu, Ming-Long Fan, Pin Su and Ching-Te Chuang,
“Static Noise Margin of Ultra-Thin-Body SOI Subthreshold SRAM Cells- An
Assessment Based on Analytical Solution of Poisson Equation,” IEEE
Transactions on Electron Devices, vol. 56, no. 9, pp. 2120-2127, September
2009.
(2) Yu-Sheng Wu, Ming-Long Fan, and Pin Su, “Investigation of Switching Time
Variations for Nanoscale MOSFETs Using the Effective Drive Current
Approach,” IEEE Electron Device Letters, vol. 31, no. 2, pp. 162-164, February
2010.
(3) Ming-Long Fan, Yu-Sheng Wu, Vita Pi-Ho Hu, Pin Su and Ching-Te Chuang,
“Investigation of Cell Stability and Write-ability of FinFET Subthreshold SRAM
Using Analytical SNM Model,” IEEE Transactions on Electron Devices, vol. 57,
no. 6, pp. 1375-1381, June 2010.
(4) Ming-Long Fan, Yu-Sheng Wu, Vita Pi-Ho Hu, Chien-Yu Hsieh, Pin Su and
Ching-Te Chuang, “Comparison of 4T and 6T FinFET SRAM Cells for
Subthreshold Operation Considering Variability – A Model-Based Approach,”
IEEE Transactions on Electron Devices, vol. 58, no. 3, pp. 609-616, March 2011.
(5) Vita Pi-Ho Hu, Ming-Long Fan, Chien-Yu Hsieh, Pin Su and Ching-Te Chuang,
“FinFET SRAM Cell Optimization Considering Temporal Variability due to
NBTI/PBTI, Surface Orientation and Various Gate Dielectrics,” IEEE
Transactions on Electron Devices, vol. 58, no. 3, pp. 805-811, March 2011.
(6) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Analysis of
Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge
Roughness, Work Function Variation and Temperature Sensitivity,” IEEE Journal
on Emerging and Selected Topics in Circuits and Systems, vol. 1, no. 3, pp.
335-342, September 2011.
(7) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Band-to-Band
Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using
Transistor Stacking,” IEEE Electron Device Letters, vol.33, no.2, pp.197-199,
February 2012.
(8) Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and Ching-Te Chuang,
“Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold
SRAMs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
vol. 20, no.7, July, pp. 1201-1210, July, 2012.

(9) Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su and Ching-Te Chuang,
“Analysis of Single Trap Induced Random Telegraph Noise on FinFET Devices,
6T SRAM Cell and Logic Circuits,” IEEE Transactions on Electron Devices, vol.
59, no. 8, pp. 2227-2234, August 2012.
(10)Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su and Ching-Te Chuang,
“Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM
Applications,” IEEE Transactions on Circuits and Systems – II Express Briefs,
vol. 59, no. 12, pp. 878-882, December 2012.
(11)Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Threshold
Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells,”
IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 147-152, January
2013.
(12)Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and Ching-Te Chuang,
“Design and Analysis of Robust Tunneling FET SRAM,” IEEE Transaction on
Electron Devices, vol. 60, no. 3, pp.1092-1098, March 2013.
(13)Shao-Heng Chou, Ming-Long Fan, and Pin Su, “Investigation and Comparison
of Work Function Variation for FinFET and UTB SOI Devices Using Voronoi
Approach,” IEEE Transaction on Electron Devices, vol. 60, no. 4, pp.1485-1489,
April 2013.
“Analysis of Single-Trap-Induced Random Telegraph Noise and Its Interaction
With Work Function Variation for Tunnel FET,” IEEE Transaction on Electron
Devices, vol. 60, no. 6, pp. 2038-2044, June 2013.
(15)Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Threshold
Voltage Design of UTB SOI SRAM with Improved Stability/Variability for
Ultra-Low Voltage Near Subthreshold Operation,” IEEE Transactions on
Nanotechnology, vol. 12, no. 4, pp. 524-531, July 2013.
(16)Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Comparative
Leakage Analysis of GeOI FinFET and Ge Bulk FinFET,” IEEE Transaction on
Electron Devices, vol. 60, no. 10, pp. 3596-3600, October 2013.
(17)Ming-Long Fan, Shao-Yu Yang, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su and
Ching-Te Chuang, “Single-Trap-Induced Random Telegraph Noise for FinFET,
Si/Ge Nanowire FET, Tunnel FET, SRAM and Logic Circuits,” Microelectronics
Reliability, vol. 54, issue 4, pp. 698-711, April 2014 (Invited).
“Evaluation of Sub-0.2V High-Speed Low-Power Circuits Using Hetero-Channel
MOSFET and Tunneling FET Devices,” IEEE Transactions on Circuits and
Systems – I, vol. 61, no. 12, pp. 3339-3347, December 2014.

“Stability and Performance Optimization of Hetero-Channel Monolithic 3D
SRAM Cells Considering Interlayer Coupling,” IEEE Transaction on Electron
Devices, vol. 61, no. 10, pp. 3448-3455, October 2014.
(20)Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Chih-Wei Hsu, Pin Su and
Ching-Te Chuang, “Investigation of Backgate-Biasing Effect for Ultra-Thin-Body
III-V Heterojunction Tunnel FET,” IEEE Transaction on Electron Devices, vol.
62, no. 1, pp. 107-113, January 2015.
(21)Ko-Chun Lee, Ming-Long Fan and Pin Su, “Investigation and Comparison of
Analog Figures-of-Merit for TFET and FinFET Considering Work-Function
Variation,” Microelectronics Reliability, vol. 55, issue 2, pp. 332-336, January
2015.
“Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and
Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits,” IEEE Journal
on Emerging and Selected Topics in Circuits and Systems, vol. 4, no. 4, pp.
389-399, December 2014.
International Conference:
“Investigation of Static Noise Margin of Ultra-Thin-Body SOI SRAM Cells in
Subthreshold Region Using Analytical Solution of Poisson's Equation,”
Proceedings of the IEEE 2009 VLSI-TSA International Symposium on VLSI
Technology, Systems and Applications, Hsinchu, Taiwan, April 2009, pp.
115-116.
(2) Jack Jyun-Yan Kuo, Ming-Long Fan, and Pin Su, “Investigation of Mismatching
Properties in Nanoscale MOSFETs with Symmetric/Asymmetric Halo Implant,”
Proceedings of the 2009 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan,
June 2009, pp. 127-128.
(3) Yu-Sheng Wu, Ming-Long Fan, and Pin Su, “Investigation of Switching Time
Variations for FinFET and Bulk MOSFETs Using the Effective Drive Current
Approach,” Proceedings of the 2009 Silicon Nanoelectronics Workshop (SNW),
Kyoto, Japan, June 2009, pp. 7-8.
“Design and Analysis of Ultra-Thin-Body SOI Based Subthreshold SRAM,”
International Symposium on Low Power Electronics and Design (ISLPED 2009),
San Francisco, California, USA, August 2009, pp. 9-14.

(5) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Impact of Work
Function Design on the Stability and Performance of Ultra-Thin-Body SOI
Subthreshold SRAM,” Proceedings of the 39th European Solid-State Device
Research Conference (ESSDERC 2009), Athens, Greece, September 2009, pp.
145-148.
“Investigation of Static Noise Margin of FinFET SRAM Cells in Sub-threshold
Region,” Proceedings of the 2009 IEEE International SOI Conference, Foster
City, California, USA, October 2009.
(7) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Subthreshold
SRAM with Enhanced Stability Using Ultra-Thin-Body and BOX SOI,” Extended
Abstracts of the 2009 International Conference on Solid State Devices and
Materials (SSDM), Sendai, Japan, October 2009, pp. 414-415.
“Investigation of Stability and AC Performance of Sub-threshold FinFET
SRAM,” Proceedings of the IEEE 2010 VLSI-TSA International Symposium on
VLSI Technology, Systems and Applications, Hsinchu, Taiwan, April 2010, pp.
66-67.
(9) Yu-Sheng Wu, Ming-Long Fan, and Pin Su, “Impact of Surface Orientation on
Vth Variability of FinFET,” Proceedings of the 2010 Silicon Nanoelectronics
Workshop (SNW), Honolulu, Hawaii, USA, June 2010, pp. 75-76.
“FinFET SRAM Cell Optimization Considering Temporal Variability Due to
NBTI/PBTI and Surface Orientation,” Proceedings of the 15th International
Conference on Simulation of Semiconductor Processes and Devices (SISPAD),
Bologna, Italy, September 2010, pp. 269-272.
(11) Ming-Long Fan, Vita Pi-Ho Hu, Chien-Yu Hsieh, Pin Su and Ching-Te Chuang,
“Subthreshold FinFET SRAM Cell Optimization Considering Surface-Orientation
Dependent Variability,” Proceedings of the 40th European Solid-State Device
Research Conference (ESSDERC), Seville, Spain, September 2010, pp. 198-201.
“High-k Metal Gate FinFET SRAM Cell Optimization Considering Variability
Due to NBTI/PBTI and Surface Orientation,” Extended Abstracts of the 2010
International Conference on Solid State Devices and Materials (SSDM), Tokyo,
Japan, September 2010, pp. 1020-1021.
(13) Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and Ching-Te Chuang,
“Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMs,”
Proceedings of the 2010 IEEE International SOI Conference, San Diego,

California, USA, October 2010.
(14) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Evaluation of
Static Noise Margin and Performance of 6T FinFET SRAM Cells With
Asymmetric Gate to Source/Drain Underlap Devices,” Proceedings of the 2010
IEEE International SOI Conference, San Diego, California, USA, October 2010.
(15) Yin-Nien Chen, Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and
Ching-Te Chuang, “Disturb-Free Independently-Controlled-Gate 7T FinFET
SRAM Cell,” Proceedings of the IEEE 2011 VLSI-TSA International Symposium
on VLSI Technology, Systems and Applications, Hsinchu, Taiwan, April 2011.
(16) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Leakage-Delay
Analysis of Ultra-Thin-Body GeOI Devices and Logic Circuits,” Proceedings of
the IEEE 2011 VLSI-TSA International Symposium on VLSI Technology, Systems
and Applications, Hsinchu, Taiwan, April 2011.
(17) Yin-Nien Chen, Chien-Yu Hsieh, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and
Ching-Te Chuang, “Impacts of Intrinsic Device Variations on the Stability of
FinFET Subthreshold SRAMs,” Proceedings of the 2011 IEEE International
Conference on IC Design and Technology (ICICDT), Kaohsiung, Taiwan, May
2011.
(18) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Variability
Analysis of UTB SOI Subthreshold SRAM Considering Line-Edge Roughness,
Work Function Variation and Temperature Sensitivity,” Proceedings of the 2011
IEEE International Conference on IC Design and Technology (ICICDT),
Kaohsiung, Taiwan, May 2011.
Power-Performance for Ultra-Thin-Body GeOI Logic Circuits,” International
Symposium on Low Power Electronics and Design (ISLPED 2011), Fukuoka,
Japan, August 2011, pp. 115-120.
(20) Barney Ken-Yen Lu, Ming-Long Fan, and Pin Su, “Impact of Aspect Ratio on
the Subthreshold RTN Amplitude of Multi-Gate MOSFETs,” Extended Abstracts
of the 2011 International Conference on Solid State Devices and Materials
(SSDM), Nagoya, Japan, September 2011, pp. 84-85.
“Impact of Single Trap Induced Random Telegraph Noise on FinFET Device and
SRAM Stability,” Proceedings of the 2011 IEEE International SOI Conference,
Tempe AZ, USA, October 2011.
(22) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Comprehensive
Analysis of UTB GeOI Logic Circuits and 6T SRAM Cells Considering
Variability and Temperature Sensitivity,” 2011 International Electron Devices

Meeting (IEDM), Washington DC, USA, December 2011, pp. 753-756.
“Comparison of Differential and Large-Signal Sensing Scheme for
Subthreshold/Superthreshold FinFET SRAM Considering Variability,”
Technology, Systems and Applications, Hsinchu, Taiwan, April 2012.
(24) Chun-Hsien Chiang, Ming-Long Fan, Jack Jyun-Yan Kuo, and Pin Su, “Body
Effect Induced Variability in Bulk Tri-gate MOSFETs,” Proceedings of the IEEE
2012 VLSI-TSA International Symposium on VLSI Technology, Systems and
Applications, Hsinchu, Taiwan, April 2012.
(25) Ming-Fu Tsai, Barney Kun-Yen Lu, Ming-Long Fan, Chia-Hao Pao, Yin-Nien
Chen, Vita Pi-Ho Hu, Pin Su and Ching-Te Chuang, “Impacts of Wire-LER on
Nanowire MOSFET Devices, Subthreshold SRAM and Logic Circuits,”
Technology, Systems and Applications, Hsinchu, Taiwan, April 2012.
“Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and
Logic Circuits,” Proceedings of the 2012 IEEE International Reliability Physics
Symposium (IRPS), Anaheim, CA, USA, April 2012, pp. CR.1.1-CR.1.6.
(27) Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu,
Pin Su and Ching-Te Chuang, “Impacts of Random Telegraph Noise on the
Analog Properties of FinFET and Trigate Devices and Widlar Current Source,”
Proceedings of the 2012 IEEE International Conference on IC Design and
Technology (ICICDT), Texas, USA, May 2012.
(28) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Stability and
Performance Optimization of InGaAs-OI and GeOI Heterochannel SRAM Cells,”
Proceedings of the 42nd European Solid-State Device Research Conference
(ESSDERC), Bordeaux, France, September 2012, pp. 77-80.
(29) Yin-Nein Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and Ching-Te Chuang,
“A Comparative Analysis of Tunneling FET Circuit Switching Characteristics and
SRAM Stability and Performance,” Proceedings of the 42nd European Solid-State
Device Research Conference (ESSDERC), Bordeaux, France, September 2012, pp.
157-160.
(30) Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nein Chen, Ko-Chun Lee, Pin Su and
Ching-Te Chuang, “Variability Analysis of Sense Amplifier for Subthreshold
Ultra-Thin-Body SOI SRAM Applications,” Extended Abstracts of the 2012
International Conference on Solid State Devices and Materials (SSDM), Kyoto,

(31) Shao-Heng Chao, Ming-Long Fan, and Pin Su, “Investigation and Comparison
of Work Function Variation for FinFET and Ultra-Thin-Body SOI Devices Using
a Voronoi Approach,” Extended Abstracts of the 2012 International Conference
on Solid State Devices and Materials (SSDM), Kyoto, Japan, September 2012, pp.
785-786.
(32) Chia-Hao Pao, Ming-Long Fan, Ming-Fu Tsai, Yin-Nien Chen, Vita Pi-Ho Hu,
Pin Su and Ching-Te Chuang, “A Comprehensive Comparative Analysis of
FinFET and Trigate Devices, SRAM and Logic Circuits,” 2012 IEEE Asia Pacific
Conference on Circuits and Systems (APCCAS), Kaohsiung, Taiwan, December,
2012, pp. 463-466.
(33) Ming-Fu Tsai, Jen-Huan Tsai, Ming-Long Fan, Pin Su and Ching-Te Chuang,
“Variation Tolerant CLSAs for Nanoscale Bulk-CMOS and FinFET SRAM,”
2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS),
Kaohsiung, Taiwan, December, 2012, pp. 471-474.
(34) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Device Design
and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and
Bulk Substrates,” Proceedings of the 2013 International Symposium on Quality
Electronic Design (ISQED), Santa Clara, CA, USA, March 2013, pp. 347-352.
“Investigation of Single-Trap-Induced Random Telegraph Noise for Tunneling
FET Devices, 8T SRAM Cell, and Sense Amplifiers,” Proceedings of the 2013
IEEE International Reliability Physics Symposium (IRPS), Monterey, CA, USA,
April 2013, pp. CR.1.1-CR.1.6.
Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to
Source/Drain Underlap Devices,” Proceedings of the IEEE 2013 VLSI-TSA
International Symposium on VLSI Technology, Systems and
(37) Ming-Fu Tsai, Ming-Long Fan, Chia-Hao Pao, Yin-Nien Chen, Vita Pi-Ho Hu,
Pin Su and Ching-Te Chuang, “Design and Optimization of 6T SRAM Using
Vertically Stacked Nanowire MOSFETs,” Proceedings of the IEEE 2013
VLSI-TSA International Symposium on VLSI Technology, Systems and
(38) Jack Jyun-Yan Kuo, Ming-Long Fan, Wei Lee, and Pin Su, “Source/Drain
Series Resistance Induced Feedback Effect on Drain Current Mismatch and Its
Implication,” Proceedings of the IEEE 2013 VLSI-TSA International Symposium
on VLSI Technology, Systems and Applications, Hsinchu, Taiwan, April 2013.
(39) Shao-Yu Yang, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and

Ching-Te Chuang, “Impacts of Single Trap Induced Random Telegraph Noise on
Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits,” Proceedings of
the 2013 IEEE International Conference on IC Design and Technology
(ICICDT), Pavia, Italy, May 2013, pp. 61-64.
(40) Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and Ching-Te Chuang,
“Investigation of Tunneling FET Device Designs for Improving Circuit Switching
Performance and Energy,” Extended Abstracts of the 2013 International
Conference on Solid State Devices and Materials (SSDM), Fukuoka,
(41) Vita Pi-Ho Hu, Hsin-Hung Shen, Ming-Long Fan, Pin Su and Ching-Te
Chuang, “Leakage-Delay Analysis of InxGa1-xAs-OI FinFETs for Logic
Applications,” Extended Abstracts of the 2013 International Conference on Solid
State Devices and Materials (SSDM), Fukuoka, Japan, September 2013, pp.
710-711.
(42) Ko-Chun Lee, Ming-Long Fan, and Pin Su, “Comparison of Analog FOM for
TFET and FinFET Considering Work Function Variation,” Extended Abstracts of
the 2013 International Conference on Solid State Devices and Materials (SSDM),
Fukuoka, Japan, September 2013, pp. 712-713.
Transient Voltage Collapse Write-Assist for GeOI and SOI FinFET SRAM
Cells,” Proceedings of the 2013 IEEE SOI-3D-Subthreshold Microelectronics
Technology Unified Conference (IEEE S3S), Monterey, California, October 2013.
“Comprehensive Analysis of Ultra-Thin-Body MOSFETs for Monolithic 3D
Logic Circuits With Interlayer Coupling,” Proceedings of the 2013 International
Semiconductor Device Research Symposium (ISDRS), Maryland, USA, December
2013.
“Stability/Performance Assessment of Monolithic 3D 6T/8T SRAM Cells
Considering Transistor-Level Interlayer Coupling,” Proceedings of the 2014
International Symposium on VLSI Technology, Systems and Applications
(VLSI-TSA), Hsinchu, Taiwan April 2014, pp. 107-108.
Read- and Write-Assist Circuits for GeOI FinFET 6T SRAM Cells,” Proceedings
of the 2014 IEEE International Symposium on Circuits and Systems (ISCAS),
Melbourne, Australia, June 2014, pp. 1122-1125.
(47) Ko-Chun Lee, Ming-Long Fan, and Pin Su, “Comparison of Analog FOM for
TFET and FinFET Considering Line-Edge Roughness,” 3rd
International

Symposium on Next-Generation Electronics (ISNE 2014), Taoyuan, Taiwan, May
2014, D2-3.
“Investigation and Optimization of Monolithic 3D Logic Circuits and SRAM
Cells Considering Interlayer Coupling,” Proceedings of the 2014 IEEE
International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia,
June 2014, pp. 1130-1133.
(49) Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and Ching-Te Chuang,
“Ultra-Low Voltage Mixed TFET-MOSFET 8T SRAM Cell,” International
Symposium on Low Power Electronics and Design (ISLPED 2014), San Diego,
California, USA, August 2014, pp. 255-258.
(50) Chih-Wei Hsu, Ming-Long Fan, and Pin Su, “Investigation and Mitigation of
Work-Function Variation for III-V Heterojunction Tunnel FET,” Extended
Abstracts of the 2014 International Conference on Solid State Devices and
Materials (SSDM), Tsukuba, Japan, September 2014, pp. 224-225.
(51) Kuan-Chin Yu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Leakage-Delay
Analysis of Monolithic 3D Logic Circuits Using Ultra-Thin-Body InGaAs/Ge
MOSFETs Considering Interlayer Electrical Coupling,” Extended Abstracts of the
2014 International Conference on Solid State Devices and Materials (SSDM),
Tsukuba, Japan, September 2014, pp. 994-995.
(52) Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and
Ching-Te Chuang, “Impact of Work Function Variation and Line-Edge
Roughness on TFET and FinFET Devices and Logic Circuits,” Proceedings of the
2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified
Conference (IEEE S3S), San Francisco, California, October 2014.
(53) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Stability
Analysis for UTB GeOI 6T SRAM Cells considering NBTI and PBTI,”
Proceedings of the 2015 International Symposium on VLSI Technology, Systems
and Applications (VLSI-TSA), Hsinchu, Taiwan April 2015 (accepted).
(54) Kuan-Chin Yu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Analysis of
Monolithic 3D 6T SRAM using Ultra-Thin-Body InGaAs/Ge MOSFETs
considering Interlayer Coupling,” Proceedings of the 2015 International
Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu,
Taiwan April 2015 (accepted).
(55) Vita Pi-Ho Hu, Ming-Long Fan, Pin Su and Ching-Te Chuang, “Impacts of
NBTI and PBTI on Ultra-Thin-Body GeOI 6T SRAM Cells,” Proceedings of the
2015 IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon,
Portugal, June 2015 (accepted).

(56) Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su and
Ching-Te Chuang, “Evaluation of TFET and FinFET Devices and 32-Bit CLA
Circuits Considering Work Function Variation and Line-Edge
Roughness,” Proceedings of the 2015 IEEE International Symposium on Circuits
and Systems (ISCAS), Lisbon, Portugal, June 2015 (accepted).
Honor:
(1) (2009 SOI Conference oral presentation) 2009/10/5~2009/10/8, analytical
model and design for subthreshold FinFET SRAM with financial support from
the ATU Program, Ministry of Education, Taiwan.
(2) (2010 ESSDERC oral presentation) 2010/9/13~2010/9/17, stability
optimization of subthreshold FinFET SRAM cell using surface orientation with
financial support from the ATU Program, Ministry of Education, Taiwan
(http://www.essderc2010.org/)。
(3) (2011 SOI Conference oral presentation) 2011/10/3~2011/10/6, present the
impact of random telegraph noise on FinFET Device and circuits with financial
support from the ATU Program, Ministry of Education, Taiwan.
(4) (2012 SSDM oral presentation) 2012/9/25~2012/9/27, assess variability
analysis for UTB SOI based SRAM sense amplifiers with financial support from
the Ministry of Science and Technology, Taiwan.
(5) (2013 ISDRS oral presentation) 2013/12/11~2013/12/13, present design and
optimization of monolithic 3D logic circuit (http://www.isdrs2013.org/) with
financial support from the ATU Program, Ministry of Science and Technology,
Taiwan.
(6) (MOST I-RiCE (International Research-intensive Center of Excellence) and
NCTU-TSMC Joint Research Center 2013 Best Student Poster Award)
Ming-Long Fan and Pin Su, “Investigation of Single-Trap-Induced Random
Telegraph Noise and Work Function Variation for Tunnel FET (TFET),”
December, 2013.
(7) (2014 TSIA DOCTORAL RESEARCH AWARD) Student: Ming-Long Fan，
Advisor: Pin Su and Chin-Te Chuang, March, 2014.
(8) (2014 ISCAS oral presentation) 2014/6/1~2014/6/5, present optimization of
UTB SOI MOSFETs for monolithic 3D logic and SRAM circuits
(http://iscas2014.org/) Finalist for the ISCAS 2014 Student Best Paper Award。

Patent:
(1) ��景德、謝建宇、范銘隆、胡壁合、蘇彬, “以史密特觸發器為基礎的鰭狀��
效電晶體靜態隨機存取記憶體,” 申請案號: 99123534,申請日期: 99.07.16,中
華民國專利。證書號: I455129，保護期限: 2014/10/1-2030/7/15。
(2) 莊景德、謝建宇、范銘隆、胡壁合、蘇彬, “Schmitt Trigger-Based FinFET SRAM
Cell,” USA Patent 8,169,814 B2, issued May 1, 2012, 保護期限 :
2010/9/7-2030/9/8。
(3) 莊景德、陳盈年、謝建宇、范銘隆、胡壁合、蘇彬, “獨立閘極控制靜態隨機
存取記憶體,” 申請案號:100138258, 申請日期:100.10.21, 中華民國專利。公
開日:2013/05/01。公開案號:TW201317991A1。(申請中)。
(4) 莊景德、陳盈年、謝建宇、范銘隆、胡壁合、蘇彬 ,
“INDEPENDENTLY-CONTROLLED GATE,” USA Patent 8, 717,807 B2,
issued March 13, 2012, 保護期限: 2012/3/13-2033/1/4。
(5) 范銘隆、胡壁合、陳盈年、蘇彬、莊景德、潘正聖, “Novel Hybrid TFET-MOSFET
SRAM and Logic Circuit Designs,”美國專利。(交大-台積電)。(專利事務所撰
寫中)

Publications and Honors (Ming-Long Fan)

More Related Content

Publications and Honors (Ming-Long Fan)