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Nat64 server

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Janith Rukman
Janith Rukman

A hardware implementation for NAT-64 server on FPGA platform that enables IPV4 to IPV6 conversion mechanisms (vise versa)

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NAT64 SERVER Network Address Translation using vertex-5 D.P.G.S.R Fernando I.U. Liyanage J.R. Kodagoda R.S.A De Silva
Overview
Why Vertex-5  We had three choices for FPGA boards: Virtex-5,Vertex-2 & Altera  Embedded tri-mode Ethernet MAC wrapper is available only for Virtex-5 and Vertex-6  Because of which we used Virtex-5 board for our project.
Procedure Implemented the Tri-mode Ethernet MAC Wrapper Implemented the IPv4 to IPv6 conversion algorithm Implemented the IPv6 to IPv4 conversion algorithm Combine two algorithms to get the NAT64 module
Tri Mode Ethernet MAC wrapper
IPv4 to IPv6 Conversion
IPv6 to IPv4 Conversion
Header Mapping IPv4 IPv6 Ether Type: 0x0800 Ether Type:0x86dd DSCP, ECN Traffic class Header Length, Total Length Payload Length Protocol Next Header Time to Live Hop Limit Ipv4 address Ipv6 address
Static NAT Table IPv4 IPv6 1 200.2.2.2 2000:2000:2000:2000:2000:2000:2000:2 000 2 200.3.3.3 3000:3000:3000:3000:3000:3000:3000:3 000 3 200.4.4.4 4000:4000:4000:4000:4000:4000:4000:4 000 4 200.5.5.5 5000:5000:5000:5000:5000:5000:5000:5 000 Default Source 200.6.6.6 6000:6000:6000:6000:6000:6000:6000:6 Address 000 Broadcast Address 200.255.255.255 ff02::1 Multicast(to all host) 224.0.0.1 ff02::1 Multicast (to all 224.0.0.2 ff02::2 routers) unspecified 0.0.0.0 :: Loopback address 127.0.0.1 ::1
Hardware Debug Tools  ChipScope Pro Analyzer We use ChipScope Pro Inserter flow, to capture signals in ChipScope Pro
Nat64 server
 Wireshark packet sniffer software application
Issues  Virtex-5 board only has one Ethernet port though out NAT64 server needs at least two ports.  Virtex-5 device designs of Tri-mode Ethernet MAC require a Verilog LRM-IEEE 1364-2005 encryption-compliant simulator  ModelSim v6.6d  Cadence Incisive Enterprise Simulator (IES) 10.2  Synopsys VCS and VCS MX 2010.06)  Butany of those simulators are not freely available

More Related Content

Nat64 server

  • 1. NAT64 SERVER Network Address Translation using vertex-5 D.P.G.S.R Fernando I.U. Liyanage J.R. Kodagoda R.S.A De Silva
  • 3. Why Vertex-5  We had three choices for FPGA boards: Virtex-5,Vertex-2 & Altera  Embedded tri-mode Ethernet MAC wrapper is available only for Virtex-5 and Vertex-6  Because of which we used Virtex-5 board for our project.
  • 4. Procedure Implemented the Tri-mode Ethernet MAC Wrapper Implemented the IPv4 to IPv6 conversion algorithm Implemented the IPv6 to IPv4 conversion algorithm Combine two algorithms to get the NAT64 module
  • 5. Tri Mode Ethernet MAC wrapper
  • 6. IPv4 to IPv6 Conversion
  • 7. IPv6 to IPv4 Conversion
  • 8. Header Mapping IPv4 IPv6 Ether Type: 0x0800 Ether Type:0x86dd DSCP, ECN Traffic class Header Length, Total Length Payload Length Protocol Next Header Time to Live Hop Limit Ipv4 address Ipv6 address
  • 9. Static NAT Table IPv4 IPv6 1 200.2.2.2 2000:2000:2000:2000:2000:2000:2000:2 000 2 200.3.3.3 3000:3000:3000:3000:3000:3000:3000:3 000 3 200.4.4.4 4000:4000:4000:4000:4000:4000:4000:4 000 4 200.5.5.5 5000:5000:5000:5000:5000:5000:5000:5 000 Default Source 200.6.6.6 6000:6000:6000:6000:6000:6000:6000:6 Address 000 Broadcast Address 200.255.255.255 ff02::1 Multicast(to all host) 224.0.0.1 ff02::1 Multicast (to all 224.0.0.2 ff02::2 routers) unspecified 0.0.0.0 :: Loopback address 127.0.0.1 ::1
  • 10. Hardware Debug Tools  ChipScope Pro Analyzer We use ChipScope Pro Inserter flow, to capture signals in ChipScope Pro
  • 12.  Wireshark packet sniffer software application
  • 13. Issues  Virtex-5 board only has one Ethernet port though out NAT64 server needs at least two ports.  Virtex-5 device designs of Tri-mode Ethernet MAC require a Verilog LRM-IEEE 1364-2005 encryption-compliant simulator  ModelSim v6.6d  Cadence Incisive Enterprise Simulator (IES) 10.2  Synopsys VCS and VCS MX 2010.06)  Butany of those simulators are not freely available

Editor's Notes

  1. Monahriliyapaaannn
  2. According to the slides, given by Dr. Pasqual, there are 3 types of FPGAtri-mode Ethernet MAC wrapper is free
  3. We have to configure the TEMAC wrapper
  4. The generated example design for this OpenSparc board will not work if implemented and downloaded to the board as is. We must make some configuration changes in the example design so that it works on the OpenSparc board. This is the most hardest part in our project
  5. This is the timing diagramFor each ipv4 packet received, NAt64 send ipv6 packet after delaying 36 bytesData and FCS field is delayed by (76-x) bytes
  6. This is the timing diagramFor each ipv6 packet received, NAt64 send ipv4 packet after delaying 36 bytesData and FCS field is delayed by 16 bytes
  7. ‘Ether type’ in ethernet header is used to determine whether this packet is ipv4 or ipv6How ipv4 packets and ipv6 packets are mapped each other
  8. There are twomethosChipScope Pro Inserter flow (which is easy)(which we use)ChipScope Pro Core Generator flow
  9. So, the single Ethernet port has to represent IPv4 network and IPv6 networkBecause of unavailability of functional and timing simulations, we have to rely on the hardware debug tools (ChipScope Pro Analyzer and wireshark). This make the project extremely difficult and time consuming (synthesizing, implementing and generating a programming file takes lots of time )