Is Advanced Verification for FPGA based Logic needed
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The document discusses the need for advanced verification in FPGA-based logic design. It argues that FPGAs have similar complexity issues as ASICs for high-quality applications. While FPGAs allow for reprogramming, current FPGA verification relies on manual testing and debugging which has long cycle times and lacks visibility into test quality. The document proposes a new coverage-driven verification methodology using constrained random testing to improve productivity, quality, and certification. It demonstrates this methodology and discusses how it can find more bugs than manual testing while being less expensive.
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Is Advanced Verification for FPGA based Logic needed
- 1. Is Advanced Verification for FPGA based Logic really needed? By Nir Weintroub Verisense Ltd. May 2, 2012 4, 2011
- 2. Is FPGA Design Simpler than ASIC Design ? NO ! FPGA has similar complexity issues to ASIC: • High-complexity applications • Large gate-count applications • High-quality application May 4, 2011 Verisense Ltd. 2
- 3. So why are ASIC verification Methodologies much more progressive than FPGA ones ??? May 4, 2011
- 4. FPGA Vs. ASIC • Biggest advantage: Re-programmable – Fix bugs – Phased product releases – Prototype ASICs – Evolve with specifications – Field upgrades May 4, 2011 Verisense Ltd. 4
- 5. FPGA Vs. ASIC • Biggest disadvantage: Re-programmable – Relied on to fix bugs – Promotes trial-and-error engineering May 4, 2011 Verisense Ltd. 5
- 6. FPGA Verification Current Problem • Productivity issues : – Lab testing has long cycle time(debug +reprogramming) – direct testing – Major Manual effort May 4, 2011
- 7. FPGA Verification Current Problem • Quality issues : – Using direct testing, One can only check scenarios that he/she think of – Did we checked everything ? No visibility of the real test quality – Certification (e.g. DO 254) ! May 4, 2011
- 8. Here is what we are looking for …. • Minimize cycle time • Maximize quality • Certify conformance (e.g. DO254) • Maximum visibility of the testing coverage May 4, 2011 Verisense Ltd. 8
- 9. Here is what we are looking for …(Cont.) • Debug environment • Easy recreation of issues founded in the LAB May 4, 2011 Verisense Ltd.
- 10. What is the New Verification Methodology? CDV : Coverage Driven Verification The idea: The Verification environment is an automatic machine that uses constrained random generation of scenarios and configurations in order to exercise the design and verify (automatically) that the design is working according to the architecture specification. Verification is done after achieving pre-defined coverage goals May 4, 2011 Verisense Ltd.
- 11. What are the Coverage Goals? Definition of the functionality required to be tested to achieve the quality goals May 4, 2011 • • Checking
- 12. For Example : Pseudo image processing design with the next features : Dut • Pixel Input 8-10-12 bit • Pixel manipulation : #1 #2 #3 • “7-boom” • Bitwise “not” CPU I/F • Bitwise “or” and “and” • Simple Data/Valid protocol • All three phases are the same • Instead Matlab , Perl May 4, 2011 Verisense Ltd.
- 13. And Now : The DEMO ! May 4, 2011 Verisense Ltd.
- 14. Constrained Random Generation ? – Improves test coverage by automatically generating values. – Reduces number of tests since a single test can check many scenarios. – Random generation is not so useful without constraints. May 4, 2011
- 15. So, How will our new environment will look like ?! Given : DUT SB SB SB #1 #2 #3 Matlab Model Matlab #1 Matlab #2 Matlab #3 TEST FLOW Pre-Run Gen Mon Mon Mon #1 #2 #3 Dut Matlab Run #1 #2 #3 Simulation CPU I/F Test End PASSED/FAIL May 4, 2011
- 16. Now, Do we have all we need ? May 4, 2011
- 17. Coverage measurement tool This independent tool will answer the next question : – Which of the coverage goals was achieved ? – Which functionality we didn’t check yet ? – Project progress ? 20% , 80% – Can we get into lab ? – If yes, What are the exact features we can check in lab ? May 4, 2011
- 18. And Now : The DEMO ! Coverage results are not perfect !!! May 4, 2011
- 19. And Now : The DEMO ! Verisense Ltd. 19 Let’s analyze the ‘holes’ May 4, 2011
- 20. And Now : The DEMO ! Now , Integration is waiting for our FPGA. May 4, 2011 Verisense Ltd. 20
- 21. What is about the cost ?bug What the cost of one in the lab ? Debug : at least 5 hours of at least 2people Recompile : another 5 hours Re-Run : another 1 hours May 4, 2011 Verisense Ltd. 21
- 22. Bottom Line : 1 bug =~ 2 WD 30 bugs =~ 60WD => 3 working Months May 4, 2011 Verisense Ltd. 22
- 23. Advanced Verification is less expensive will catch much more than 30 bugs ! May 4, 2011 Verisense Ltd. 23
- 24. What is the cost of one bug that was not detected in the lab? May 4, 2011 Verisense Ltd. 24
- 25. Is Advanced Verification for FPGA based Logic really needed? Of Course ! May 2, 2012 4, 2011
- 26. Verisense Background • The largest design and verification services company in Israel • Company founded in 2007 • Managed by seasoned managers with many years experience in the industry • Currently employ over 60 employees and growing • Customers to date include: May 4, 2011 Verisense Confidential
- 27. And remember : May 4, 2011
- 28. 1974 Brian W. Kernighan • Debugging is twice as hard as writing the code in the first place. Therefore, if you write the code as cleverly as possible, you are, by definition, not smart enough to debug it. May 4, 2011
- 29. The END ! May 4, 2011