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I/O System

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Nagarajan
Nagarajan

The document discusses input/output (I/O) processing and the role of the operating system in managing I/O operations and devices. It covers I/O hardware components like ports, buses, and controllers. It also describes the different models for interaction between I/O controllers and CPUs, including polling, interrupts, and direct memory access (DMA). Finally, it discusses I/O application interfaces and blocking vs non-blocking I/O.

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INPUT / OUTPUT PROCESSING MAIN JOB OF COMPUTER?
ROLE OF OPERATING SYSTEM? To manage and control I/O operations and I/O devices. TOPICS COVERED I/O Hardware I/O Application Interface
 
I/O HARDWARE PORT A Connection Point through which a device communicates with a computer system by sending signals
I/O HARDWARE BUS A common set of wires used by devices for communication(daisy chain or shared direct access) Example PCI , ISA, SCSI
I/O HARDWARE CONTROLLER A collection of electronics that can operate a port,a bus,or a device Serial port controller, SCSI controller, IDE controller The processor give commands and data to a controller to accomplish an I/O transfer Direct I/O instructions Memory-mapped I/O Direct I/O + memory mapped I/O
Controller… I/O controller has 4 types of registers Status registers - also known as flag register or condition code register (CCR) ) is a collection of flag bits for a processor. Control registers- - is a processor register which changes or controls the general behavior of a CPU or other digital device. Data-in registers -Used by Host to get Input Data-out registers -Used by Host to send output
PCI BUS STRUCTURE
A PCI Bus consists of Serial Port Controller, SCSI Bus controller etc., A serial port controller is a simple device controller and it is a chip or portion of a chip in the computer. It controls the signal s on the wires of a serial port. SCSI bus controller is contrast to serial port controller as SCSI protocol is complex . SCSI bus controller is frequently implemented as a separate circuit board or a host adapter that plugs into the computer. It consists of a processor,Microcode and Private memory to enable it to process SCSI protocol messages PCI BUS STRUCTURE
Three interaction models between I/O controllers and CPUs Polling Interrupt Direct Memory Access(DMA) I/O HARDWARE
POLLING Polling refers to the situation where a device is repeatedly checked for readiness. Is reasonable only if the device and controller are fast. EXAMPLE -> 2 bits are used -> The controller indicates its state through the busy bit in the status register. -> The controller sets the busy bit when it is busy working and clears the busy bit when it is ready to accept the next command
Example continued… The host signals its wishes via the command-ready bit in the command register. The host sets the command ready bit when a command is available for the controller to execute. Process 1.The host repeatedly reads the busy bit until that bit becomes clear. 2.The host sets the write bit in the command register and writes a byte into the data out register 3.The host sets the command ready bit
PROCESS contd… 4.When the controller notices the command ready bit is set it sets the busy bit. 5.The controller reads the command register and sees the write command. 6.It reads the data out register to get the byte and does the I/O to device. 7.The controller clears the command ready bit, clears the error bit in the status register to indicate that the device. 8.I/O succeeded, and clears the busy bit to indicate that it is finished.
INTERRUPTS A Temporary stopping of a task for a while and Resuming it later CPU Interrupt request line triggered by I/O device Interrupt handler receives interrupts Maskable to ignore or delay some interrupts Interrupt vector to dispatch interrupt to correct handler Based on priority Some unmaskable, some maskable
INTERRUPTS IN SIGNAL HAS PRIORITY… INTERRUPT HANDLER ACTS LIKE CPU OTHER PROCESS
INTERRUPT Interrupt mechanism also used for exceptions and system calls Interrupt handlers can be divided into two Top half Bottom half
INTERRUPT-DRIVEN CYCLE
DIRECT MEMORY ACCESS(DMA) Used to avoid programmed I/O for large data movement Requires DMA controller for offloading of work in case of large transfers Handshaking between DMA controller and the Device Controller is performed via a pair of wires called DMA-request and DMA-acknowledge Bypasses CPU to transfer data directly between I/O device and memory
STEPS IN DMA TRANSFER
APPLICATION I/O INTERFACE The OS could be designed such that new devices can be attached to the computer without the OS being rewritten with the help of Application I/O interface. I/O system calls encapsulate device behaviors in generic classes Device-driver layer hides differences among I/O controllers from kernel Devices vary in many dimensions Character-stream or block Sequential or random-access Sharable or dedicated Speed of operation read-write, read only, or write only
BLOCK AND CHARACTER DEVICES Block devices include disk drives Commands include read, write, seek Raw I/O or file-system access Character devices include keyboards, mice, serial ports Commands include get, put Libraries layered on top allow line editing
NETWORK DEVICES Different from block and character devices to have own interface Unix and Windows NT/2000 include socket interface Separates network protocol from network operation Includes select functionality (returns information about which socket has room for data or has data available to be read)
CLOCKS AND TIMERS Programmable interval timer used for timings, periodic interrupts ioctl (on UNIX) covers odd aspects of I/O such as clocks and timers Provides three basic functions Give the Current Time Give the Elapsed Time Set a Timer to Trigger Operation
BLOCKING AND NON-BLOCKING I/O Blocking - process suspended until I/O completed Easy to use and understand Insufficient for some needs Nonblocking - I/O call returns as much as available User interface, data copy (buffered I/O) Implemented via multi-threading Returns quickly with count of bytes read or written Asynchronous - process runs while I/O executes /O subsystem signals process when I/O completed
 
 

More Related Content

I/O System

  • 1.  
  • 2. INPUT / OUTPUT PROCESSING MAIN JOB OF COMPUTER?
  • 3. ROLE OF OPERATING SYSTEM? To manage and control I/O operations and I/O devices. TOPICS COVERED I/O Hardware I/O Application Interface
  • 4.  
  • 5. I/O HARDWARE PORT A Connection Point through which a device communicates with a computer system by sending signals
  • 6. I/O HARDWARE BUS A common set of wires used by devices for communication(daisy chain or shared direct access) Example PCI , ISA, SCSI
  • 7. I/O HARDWARE CONTROLLER A collection of electronics that can operate a port,a bus,or a device Serial port controller, SCSI controller, IDE controller The processor give commands and data to a controller to accomplish an I/O transfer Direct I/O instructions Memory-mapped I/O Direct I/O + memory mapped I/O
  • 8. Controller… I/O controller has 4 types of registers Status registers - also known as flag register or condition code register (CCR) ) is a collection of flag bits for a processor. Control registers- - is a processor register which changes or controls the general behavior of a CPU or other digital device. Data-in registers -Used by Host to get Input Data-out registers -Used by Host to send output
  • 10. A PCI Bus consists of Serial Port Controller, SCSI Bus controller etc., A serial port controller is a simple device controller and it is a chip or portion of a chip in the computer. It controls the signal s on the wires of a serial port. SCSI bus controller is contrast to serial port controller as SCSI protocol is complex . SCSI bus controller is frequently implemented as a separate circuit board or a host adapter that plugs into the computer. It consists of a processor,Microcode and Private memory to enable it to process SCSI protocol messages PCI BUS STRUCTURE
  • 11. Three interaction models between I/O controllers and CPUs Polling Interrupt Direct Memory Access(DMA) I/O HARDWARE
  • 12. POLLING Polling refers to the situation where a device is repeatedly checked for readiness. Is reasonable only if the device and controller are fast. EXAMPLE -> 2 bits are used -> The controller indicates its state through the busy bit in the status register. -> The controller sets the busy bit when it is busy working and clears the busy bit when it is ready to accept the next command
  • 13. Example continued… The host signals its wishes via the command-ready bit in the command register. The host sets the command ready bit when a command is available for the controller to execute. Process 1.The host repeatedly reads the busy bit until that bit becomes clear. 2.The host sets the write bit in the command register and writes a byte into the data out register 3.The host sets the command ready bit
  • 14. PROCESS contd… 4.When the controller notices the command ready bit is set it sets the busy bit. 5.The controller reads the command register and sees the write command. 6.It reads the data out register to get the byte and does the I/O to device. 7.The controller clears the command ready bit, clears the error bit in the status register to indicate that the device. 8.I/O succeeded, and clears the busy bit to indicate that it is finished.
  • 15. INTERRUPTS A Temporary stopping of a task for a while and Resuming it later CPU Interrupt request line triggered by I/O device Interrupt handler receives interrupts Maskable to ignore or delay some interrupts Interrupt vector to dispatch interrupt to correct handler Based on priority Some unmaskable, some maskable
  • 16. INTERRUPTS IN SIGNAL HAS PRIORITY… INTERRUPT HANDLER ACTS LIKE CPU OTHER PROCESS
  • 17. INTERRUPT Interrupt mechanism also used for exceptions and system calls Interrupt handlers can be divided into two Top half Bottom half
  • 19. DIRECT MEMORY ACCESS(DMA) Used to avoid programmed I/O for large data movement Requires DMA controller for offloading of work in case of large transfers Handshaking between DMA controller and the Device Controller is performed via a pair of wires called DMA-request and DMA-acknowledge Bypasses CPU to transfer data directly between I/O device and memory
  • 20. STEPS IN DMA TRANSFER
  • 21. APPLICATION I/O INTERFACE The OS could be designed such that new devices can be attached to the computer without the OS being rewritten with the help of Application I/O interface. I/O system calls encapsulate device behaviors in generic classes Device-driver layer hides differences among I/O controllers from kernel Devices vary in many dimensions Character-stream or block Sequential or random-access Sharable or dedicated Speed of operation read-write, read only, or write only
  • 22. BLOCK AND CHARACTER DEVICES Block devices include disk drives Commands include read, write, seek Raw I/O or file-system access Character devices include keyboards, mice, serial ports Commands include get, put Libraries layered on top allow line editing
  • 23. NETWORK DEVICES Different from block and character devices to have own interface Unix and Windows NT/2000 include socket interface Separates network protocol from network operation Includes select functionality (returns information about which socket has room for data or has data available to be read)
  • 24. CLOCKS AND TIMERS Programmable interval timer used for timings, periodic interrupts ioctl (on UNIX) covers odd aspects of I/O such as clocks and timers Provides three basic functions Give the Current Time Give the Elapsed Time Set a Timer to Trigger Operation
  • 25. BLOCKING AND NON-BLOCKING I/O Blocking - process suspended until I/O completed Easy to use and understand Insufficient for some needs Nonblocking - I/O call returns as much as available User interface, data copy (buffered I/O) Implemented via multi-threading Returns quickly with count of bytes read or written Asynchronous - process runs while I/O executes /O subsystem signals process when I/O completed
  • 26.  
  • 27.