Q2.12: Idling ARMs in a busy world: Linux Power Management for ARM Multicluster Systems

Introduction ARM Kernel PM Plumbing Conclusion
Idling ARMs in a Busy World: Linux Power
Management for ARM multi-cluster systems
L.Pieralisi
Linaro Connect Q2-2012
L.Pieralisi ARM Ltd.
Idling ARMs in a Busy World: Linux Power Management for ARM multi-cluster systems

Outline
1 Introduction
Power Management Fundamentals
2 ARM Kernel PM Plumbing
Introduction
ARM Common PM Code
ARM core code and CPU idle improvements

Outline
1 Introduction
Introduction
ARM Common PM Code

SoC Technology and Power Consumption
Dynamic power, frequency scaling
Static (leakage) power, G (Generic) process, LP (Low Power)
process
Temperature variations
RAM retention
CPU/Cluster vs. IO devices
Need for more agressive and holistic power management

Power Managed SoC Example

Kernel Power Management Mechanics
System suspend User space forces system to sleep
Auto sleep Kernel forces system to sleep if no wake-ups
CPU idle Idle threads trigger sleep states
CPU freq CPU Frequency scaling
Runtime PM Devices Power Management
CPU hotplug Remove a CPU from the running system
Focus on CPU/Cluster Power Management (PM)
Uniﬁed code in the kernel to support saving and restoring of CPU
and Cluster state

Introduction
Outline
1 Introduction
Introduction
ARM Common PM Code

Introduction
The Need for a Common Back-end
S2RAM, CPU idle and other PM subsystems require state
save/restore
CPU architectural state (inclusive of VFP and PMU)
Peripheral state (GIC, CCI)
Cache management (clear/invalidate, pipelining)
Our Goal
Create a back-end that uniﬁes the code and caters for all
requirements

ARM Common PM Code
Outline
1 Introduction
Introduction
ARM Common PM Code

ARM Common PM Code
ARM Common PM Code Components
CPU PM notiﬁers
Local timers save/restore
cpu suspend/resume
L2 suspend/resume

ARM Common PM Code
CPU PM notiﬁers (1/3)
Introduced by C.Cross to overcome code duplication in idle
and suspend code path
CPU events and CLUSTER events
GIC, VFP, PMU

ARM Common PM Code
static int cpu_pm_notify(enum cpu_pm_event event, int nr_to_call, int *nr_calls)
{
int ret;
ret = __raw_notifier_call_chain(&cpu_pm_notifier_chain, event, NULL,
nr_to_call, nr_calls);
return notifier_to_errno(ret);
}
int cpu_pm_enter(void)
{
[...]
ret = cpu_pm_notify(CPU_PM_ENTER, -1, &nr_calls);
if (ret)
cpu_pm_notify(CPU_PM_ENTER_FAILED, nr_calls - 1, NULL);
[...]
return ret;
}
//CPU shutdown
cpu_pm_{enter,exit}();
//Cluster shutdown
cpu_cluster_pm_{enter,exit}();

ARM Common PM Code
static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
{
int i;
[...]
switch (cmd) {
case CPU_PM_ENTER:
gic_cpu_save(i);
break;
case CPU_PM_ENTER_FAILED:
case CPU_PM_EXIT:
gic_cpu_restore(i);
break;
case CPU_CLUSTER_PM_ENTER:
gic_dist_save(i);
break;
case CPU_CLUSTER_PM_ENTER_FAILED:
case CPU_CLUSTER_PM_EXIT:
gic_dist_restore(i);
break;
}
return NOTIFY_OK;
}
static struct notifier_block gic_notifier_block = {
.notifier_call = gic_notifier,
};
v7 shutdown

ARM Common PM Code
Local timers save/restore
void enter_idle(...)
{
[...]
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
[...]
cpu_do_idle();
[...]
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
[...]
}
void enter_idle(...)
{
struct tick_device *tdev = tick_get_device(cpu);
[...]
cpu_do_idle();
[...]
/* Restore the per-cpu timer event */
clockevents_program_event(tdev->evtdev, tdev->evtdev->next_event, 1);
}
Enter broacadst mode if a global timer is available
Rely on always-on ﬁrmware timer and restore timer through clock
events programming API

ARM Common PM Code
ARM v7 SMP CPU Shutdown Procedure
1 save per CPU peripherals (IC, VFP, PMU)
2 save CPU registers
3 clean L1 D$
4 clean state from L2
5 disable L1 D$ allocation
6 clean L1 D$
7 exit coherency
8 call wﬁ (wait for interrupt)

ARM Common PM Code
3 clean L1 D$
6 clean L1 D$
7 exit coherency
This is the standard procedure that must be adopted by all platforms, for
cpu switching, cpu hotplug (cache cleaning and wﬁ), suspend and idle

ARM Common PM Code
3 clean L1 D$
6 clean L1 D$
7 exit coherency
This is the standard procedure that must be adopted by all platforms, for
cpu switching, cpu hotplug (cache cleaning and wﬁ), suspend and idle
idle
notiﬁers

ARM Common PM Code
CPU suspend (1/3)
Introduced by R.King to consolidate existing (and duplicated)
code across diﬀent ARM platforms
save/restore core registers, clean L1 and some bits of L2
L2 RAM retention handling poses further challenges

ARM Common PM Code
CPU suspend (2/3)
1:1 mapping page tables cloned from init_mm
C API, generic for all ARM architectures
int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
{
struct mm_struct *mm = current->active_mm;
int ret;
if (!suspend_pgd)
return -EINVAL;
[...]
ret = __cpu_suspend(arg, fn);
if (ret == 0) {
cpu_switch_mm(mm->pgd, mm);
local_flush_tlb_all();
}
return ret;
}

ARM Common PM Code
CPU suspend (3/3)
registers saved on the stack
void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
{
*save_ptr = virt_to_phys(ptr);
/* This must correspond to the LDM in cpu_resume() assembly */
*ptr++ = virt_to_phys(suspend_pgd);
*ptr++ = sp;
*ptr++ = virt_to_phys(cpu_do_resume);
cpu_do_suspend(ptr);
}

ARM Common PM Code
CPU suspend (3/3)
L1 complete cleaning
{
*ptr++ = sp;
flush_cache_all();
}

ARM Common PM Code
CPU suspend (3/3)
L1 complete cleaning
L2 partial cleaning
{
*ptr++ = sp;
flush_cache_all();
outer_clean_range(*save_ptr, *save_ptr + ptrsz);
outer_clean_range(virt_to_phys(save_ptr),
virt_to_phys(save_ptr) + sizeof(*save_ptr));
}

ARM Common PM Code
We Are Not Done, Yet: Cache-to-Cache migration

ARM Common PM Code
SCU keeps a copy of D$ cache TAG RAMs
To avoid data traﬃc ARM MPCore systems move dirty lines across cores
Lower L1 bus traﬃc
Dirty data might be fetched from another core during
power-down sequence

ARM Common PM Code
When the suspend ﬁnisher is called L1 is still allocating
accessing current implies accessing the sp
Snooping Direct Data Intervention (DDI), CPU might pull
dirty line in
ENTRY(disable_clean_inv_dcache_v7_all)
stmfd sp!, {r4-r5, r7, r9-r11, lr}
mrc p15, 0, r3, c1, c0, 0
bic r3, #4 @ clear C bit
mcr p15, 0, r3, c1, c0, 0
isb
bl v7_flush_dcache_all
mrc p15, 0, r0, c1, c0, 1
bic r0, r0, #0x40 @ exit SMP
mcr p15, 0, r0, c1, c0, 1
ldmfd sp!, {r4-r5, r7, r9-r11, pc}
ENDPROC(disable_clean_inv_dcache_v7_all)

ARM Common PM Code
Outer Cache Management: The Odd One Out (1/2)
L310 memory mapped device (aka outer cache)
Clearing C bit does NOT prevent allocation
L2 RAM retention, data sitting in L2, not accessible if MMU
is off
If not invalidated, L2 might contain stale data if resume code
runs with L2 off before enabling it
We could clean some specific bits: which ones ?
If retained, L2 must be resumed before turning MMU on

ARM Common PM Code
Outer Cache Management: The Odd One Out (2/2)
if L2 content is lost, it must be cleaned on shutdown but can
be resumed in C
if L2 is retained, it must be resumed in assembly before calling
cpu_resume
static void __init pl310_save(void)
{
u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
L2X0_CACHE_ID_RTL_MASK;
l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
L2X0_TAG_LATENCY_CTRL);
l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
L2X0_DATA_LATENCY_CTRL);
[...]
}
//asm-offsets.c
DEFINE(L2X0_R_PHY_BASE, offsetof(struct l2x0_regs, phy_base));
DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl));
[...]

Outline
1 Introduction
Introduction
ARM Common PM Code

ARM big.LITTLE Systems
Heterogeneous system
Coherent CCI interconnect
Per-Cluster uniﬁed L2
Shared GIC 400

A15/A7 and big.LITTLE PM Requirements
Integrated L2 caches management
Inter-Cluster snoops (pipeline)
MPIDR aﬃnity levels (boot, suspend/resume)
PM QoS, CPU switching and switching latencies
CPU idle tables asymmetricity
CPU idle table switching
CPU idle cluster states
Kernel Cluster awareness
Make changes to the kernel to allow both switching and MP SW models
to run on multi-cluster systems in a power eﬃcient manner

v7 Cache Levels (1/2)
{
*ptr++ = sp;
flush_cache_all(); <- !! This call cleans all cache levels up to LoC to main memory !!
}
A15/A7 ﬂush_cache_all() also cleans L2 !
per-CPU switching/idle must not clean uniﬁed L2, not required

v7 Cache Levels (2/2)
{
*ptr++ = sp;
flush_dcache_level(flush_cache_level_cpu());
[...]
__cpuc_flush_dcache_area(ptr, ptrsz);
__cpuc_flush_dcache_area(save_ptr, sizeof(*save_ptr));
}
Introduce cache level patches into the kernel
Flush all caches to the LoU-IS

MPIDR - suspend/resume (1/2)
MPIDR[23:16]: aﬃnity level 2
MPIDRs of existing cores cannot be generated at boot unless
we probe them (pen release)
MPIDR must NOT be considered a linear index

MPIDR - suspend/resume (2/2)
ENTRY(cpu_resume)
#ifdef CONFIG_SMP
adr r0, sleep_save_sp
ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
ALT_UP(mov r1, #0)
and r1, r1, #15
ldr r0, [r0, r1, lsl #2] @ stack phys addr
#else
ldr r0, sleep_save_sp @ stack phys addr
#endif
setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
@ load phys pgd, stack, resume fn
ARM( ldmia r0!, {r1, sp, pc} )
[...]
ENDPROC(cpu_resume)
sleep_save_sp:
.rept CONFIG_NR_CPUS
.long 0 @ preserve stack phys ptr here
.endr
Create a map of MPIDR to logical indexes at boot to fetch the
proper context address

CPU idle: coupled C-states (1/3)
C.Cross code consolidating existing TI and Tegra code
shipped with current devices
Cores go idle at unrelated times that depend on the scheduler
and next event
Cluster states (whether SoC support per-CPU power rail or
not) can be attained iﬀ all cores are idle
Hotplugging CPUs to force idle is not a solution
CPU idle barrier
All CPUs request power down at almost the same time
but...if power down fails, they all have to abort together

CPUs put into a safe state and woken up (IPI) to enter
the idle barrier
int cpuidle_enter_state_coupled(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int next_state)
{
[...]
retry:
/*
* Wait for all coupled cpus to be idle, using the deepest state
* allowed for a single cpu.
*/
while (!cpuidle_coupled_cpus_waiting(coupled)) {
if (cpuidle_coupled_clear_pokes(dev->cpu)) {
cpuidle_coupled_set_not_waiting(dev->cpu, coupled);
goto out;
}
if (coupled->prevent) {
cpuidle_coupled_set_not_waiting(dev->cpu, coupled);
goto out;
}
entered_state = cpuidle_enter_state(dev, drv,
dev->safe_state_index);
}
[...]
}

...this implies enabling irqs within idle....
static int cpuidle_coupled_clear_pokes(int cpu)
{
local_irq_enable();
while (cpumask_test_cpu(cpu, &cpuidle_coupled_poked_mask))
cpu_relax();
local_irq_disable();
return need_resched() ? -EINTR : 0;
}

”Defer no time, delays have dangerous ends”
W.Shakespeare

int arch_cpuidle_enter(struct cpuidle_device *dev, ...)
{
if (arch_turn_off_irq_controller()) {
/* returns an error if an irq is pending and would be lost
if idle continued and turned off power */
abort_flag = true;
}
cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
if (abort_flag) {
/* One of the cpus didn’t turn off it’s irq controller */
arch_turn_on_irq_controller();
return -EINTR;
}
/* continue with idle */
...
}
Disable or move IRQs to one CPU
if IRQs are pending all CPUs get out of idle together

CPU idle: asymmetric tables (1/2)
Current kernel code exports a single latency table to all CPUs
b.L clusters sport asymmetric latency tables and must be
treated as such
In the switching case, idle tables must be switched at run-time
(upon notiﬁcation)
P. De Schrijver created per-CPU idle states (through a pointer
in cpuidle_device)

CPU idle: asymmetric tables (2/2)
struct cpuidle_state_parameters {
unsigned int flags;
unsigned int exit_latency; /* in US */
int power_usage; /* in mW */
unsigned int target_residency; /* in US */
unsigned int disable;
};
struct cpuidle_device {
int state_count;
struct cpuidle_state_usage states_usage[CPUIDLE_STATE_MAX];
struct cpuidle_state_kobj *kobjs[CPUIDLE_STATE_MAX];
+ struct cpuidle_state_parameters *state_parameters;
struct list_head device_list;
struct kobject kobj;
struct completion kobj_unregister;
};

CPU idle: governors and next event (1/2)
Current governors make decisions on a per-CPU basis
Diﬀerent CPUs in a cluster enter idle at arbitrary times
By the time coupled states are hit, governor decision can be
stale
Need to peek at next event to avoid initiating cluster
shutdown

CPU idle: governors and next event (2/2)
/**
* menu_select - selects the next idle state to enter
* @drv: cpuidle driver containing state data
* @dev: the CPU
*/
static int menu_select(struct cpuidle_driver *drv, struct cpuidle_device *dev)
{
[...]
/* determine the expected residency time, round up */
t = ktime_to_timespec(tick_nohz_get_sleep_length());
data->expected_us =
t.tv_sec * USEC_PER_SEC + t.tv_nsec / NSEC_PER_USEC;
[...]
/* Make sure to round up for half microseconds */
data->predicted_us = div_round64(data->expected_us * data->correction_factor[data->bucket],
RESOLUTION * DECAY);
[...]
/*
* Find the idle state with the lowest power while satisfying
* our constraints.
*/
for (i = CPUIDLE_DRIVER_STATE_START; i < drv->state_count; i++) {
struct cpuidle_state *s = &drv->states[i];
[...]
if (s->target_residency > data->predicted_us)
continue;
if (s->exit_latency > latency_req)
continue;
[...]
if (s->power_usage < power_usage) {
power_usage = s->power_usage;
data->last_state_idx = i;
data->exit_us = s->exit_latency;
}
}
return data->last_state_idx;
}

Security Management
Most of the operations carried out in secure world
Policy decisions made in Linux
ARM SMC protocol proposal under review

Putting Everything Together (1/3)
Common PM Back-End Entry
struct pm_pms {
unsigned int cluster_state;
unsigned int cpu_state;
unsigned int subsystem;
};
void enter_lowpower(unsigned int cluster_state, unsigned int cpu_state, unsigned flags)
{
int i, cpu = smp_processor_id();
struct pm_pms pms;
struct cpumask tmp;
[...]
cpu_set(cpu_index, cpuidle_mask);
cpumask_and(&tmp, &cpuidle_mask, topology_core_cpumask(cpu));
pms.cluster_state = cluster_state;
pms.cpu_state = cpu_state;
pms.subsystem = flags;
if (!cpu_weight(&tmp) == cpu_weight(topology_core_cpumask(cpu)))
pms.cluster_state = 0;
cpu_pm_enter();
if (pms.cluster_state >= SHUTDOWN)
cpu_cluster_pm_enter();
cpu_suspend(&pms, suspend_finisher);
cpu_pm_exit();
if (pms.power_state >= SHUTDOWN)
cpu_cluster_pm_exit();
cpu_clear(cpu_index, cpu_idle_mask);
return 0;
}
v7 shutdown next

int suspend_finisher(unsigned long arg)
{
struct pm_pms *pp = (struct pm_pms *) arg;
[...]
switch (pp->subsystem) {
case S2RAM:
[...]
break;
case IDLE:
[...]
break;
default:
break;
}
smc_down(...);
return 1;
}
prev

smc_down:
ldr
r0, =#SMC_NUMBER
smc #0
/*
* Pseudo code describing what secure world
* should do
*/
{
disable_clean_inv_dcache_all();
if (cluster->cluster_down && cluster->power_state == SHUTDOWN) {
flush_cache_all();
outer_flush_all();
}
normal_uncached_memory_lock();
disable_cci_snoops();
normal_uncached_memory_unlock();
power_down_command();
cpu_do_idle();
}
prev

Conclusion
PM kernel subsystems need power-down/up common back-end
Multi-cluster ARM systems require changes to core code and
CPU idle core drivers
Eﬀort will gain momentum as soon as big.LITTLE platforms
start getting merged in the mainline
Improvements for PM subsystem as a whole
Outlook
Create common back-end for S2RAM, CPU idle and other PM
subsystems using CPU suspend/resume
Integrate ARM SMC proposal
Benchmarking

THANKS !!!

Q2.12: Idling ARMs in a busy world: Linux Power Management for ARM Multicluster Systems

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Q2.12: Idling ARMs in a busy world: Linux Power Management for ARM Multicluster Systems