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Ching-Tsun Chou

Ching-Tsun Chou has nearly 20 years of experience in computer architecture, including expertise in cache coherence protocols, memory ordering, atomicity mechanisms, and virtualization. He has worked at Intel since 2013 designing atomicity mechanisms for out-of-order processors and specifying memory ordering semantics. Prior to Intel, he led the development of an FPGA-based full-system emulator at Intel and designed synchronous circuits at Fujitsu Labs of America. He has 6 granted patents, 2 pending applications, and 19 publications in the field of computer architecture.

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Ching-Tsun Chou, PhD Email: chingtsun.chou@gmail.com Mobile: (650) 283-4894 Web: http://www.linkedin.com/in/chingtsunchou Work: (408) 765-5468 Summary • Almost 20 years of deep and diverse experiences in computer architecture for both core and uncore subsystems, including cache coherence and other protocols, deadlock and starvation avoidance, memory ordering, atomicity mechanisms, transactional memory, and virtualization. • Hands-on experiences in architecture specification, both simulation-based and formal verification, performance modeling, RTL coding, FPGA prototyping, binary translation-based emulation, multi-core programming, translators from one language to another, and the debugging of complex software. • 6 patents granted, 2 patent applications pending, 19 published journal and conference papers, program committee member for ATVA, CAV, FMCAD, and TPHOLs. • Languages: C/C++ (with embedded assembly), Python, Objective Caml, Verilog and SystemVerilog, x86- 64 ISA, Murphi, SMV, HOL. • Tools: Git, Simics, QEMU, FeS2, Asim, Synopsys VCS, Verdi, Synplify, Xilinx ISE, Auspy ACE. • Wide range of interests, in particular mathematics. Industry Experience Intel Corporation • Jan 2013 to now: Designing and specifying atomicity mechanisms for an out-of-order processor core to support binary translation. Responsible for defining and specifying memory ordering semantics for atomic regions and using it to prove the correctness of code optimization transformations in binary translation. Exploring design alternatives through performance simulation. Coding and debugging of a complex simulation infrastructure involving multiple ISAs and binary translation. • 2010 to 2012: Developed a multi-threaded full-system simulator in which each virtual CPU is executed by a separate host thread and can dynamically switch between fast functional simulation based on QEMU binary translation and slower but cycle-accurate performance simulation of speculative out-of-order processors based on FeS2. The simulator can run unmodified Debian Linux and workloads in a virtual machine. • 2008 to 2010: Led the effort of building a 20-node FPGA-based full-system emulator comprising Intel MIC Knights Ferry cores on a 4x5 mesh/torus-based interconnect and demoed the emulator at 2010 Intel Developer Forum in San Francisco. The emulator ran a version of Linux and several visual computing related workloads. Also involved in the discussion which finally led to the memory ordering spec in x86 Software Developer’s Manual, volume 3. • 2005 to 2008: Responsible for the cache coherence protocol chapter of Intel QuickPath Interconnect specification. Revamped the chapter by introducing a table-based
specification methodology that has since been adopted by other projects at Intel. Responsibilities included the specification, verification, and evolution of the protocol spec based on inputs from both internal and external customers, and the generation and maintenance of validation collaterals (such as executable reference models). • 2000 to 2005: Worked with product design teams on validating RTL implementation against protocol specifications by using both simulation and formal techniques. Developed and verified several cache coherence and other protocols which were not productized. Analyzed several error correction or detection codes and wrote an internal tutorial on CRC (cyclic redundancy check). • 1997 to 2000: Worked in the formal verification team of the Merced processor design project and used both formal verification and simulation techniques to find bugs in the RTL of a processor front-end unit and the bus cluster. Wrote simulation coverage monitors. Fujitsu Labs of America • 1995 to 1997: Designed an Esterel-like synchronous language based on interval temporal logic and developed a translation from this language to synchronous circuits. Education University of California, Los Angeles - Los Angeles, CA Ph.D. and M.S. in Computer Science National Taiwan University - Taipei, Taiwan B.S. in Electrical Engineering Online Courses • Coursera, Cryptography I, taught by Dan Boneh of Stanford University, Sep 2014 Statement of Accomplishment (Grade: 100% with Distinction) • Coursera, GPS: An Introduction to Satellite Navigation, taught by Per Enge and Frank van Diggelen of Stanford University, Dec 2014 Completed, Statement of Accomplishment pending Patents: https://sites.google.com/site/chingtsunchou/patents Publications: https://sites.google.com/site/chingtsunchou/publications Google Scholar Citation: http://scholar.google.com/citations?hl=en&user=ufGYoL0AAAAJ Award: 2005 Mahboob Khan Outstanding Mentor Awards from SRC (Silicon Research Corporation. Miscellaneous • Citizenship: U.S.A. • Erdös Number = 2 (http://www.oakland.edu/enp/)

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ctchou-resume

  • 1. Ching-Tsun Chou, PhD Email: chingtsun.chou@gmail.com Mobile: (650) 283-4894 Web: http://www.linkedin.com/in/chingtsunchou Work: (408) 765-5468 Summary • Almost 20 years of deep and diverse experiences in computer architecture for both core and uncore subsystems, including cache coherence and other protocols, deadlock and starvation avoidance, memory ordering, atomicity mechanisms, transactional memory, and virtualization. • Hands-on experiences in architecture specification, both simulation-based and formal verification, performance modeling, RTL coding, FPGA prototyping, binary translation-based emulation, multi-core programming, translators from one language to another, and the debugging of complex software. • 6 patents granted, 2 patent applications pending, 19 published journal and conference papers, program committee member for ATVA, CAV, FMCAD, and TPHOLs. • Languages: C/C++ (with embedded assembly), Python, Objective Caml, Verilog and SystemVerilog, x86- 64 ISA, Murphi, SMV, HOL. • Tools: Git, Simics, QEMU, FeS2, Asim, Synopsys VCS, Verdi, Synplify, Xilinx ISE, Auspy ACE. • Wide range of interests, in particular mathematics. Industry Experience Intel Corporation • Jan 2013 to now: Designing and specifying atomicity mechanisms for an out-of-order processor core to support binary translation. Responsible for defining and specifying memory ordering semantics for atomic regions and using it to prove the correctness of code optimization transformations in binary translation. Exploring design alternatives through performance simulation. Coding and debugging of a complex simulation infrastructure involving multiple ISAs and binary translation. • 2010 to 2012: Developed a multi-threaded full-system simulator in which each virtual CPU is executed by a separate host thread and can dynamically switch between fast functional simulation based on QEMU binary translation and slower but cycle-accurate performance simulation of speculative out-of-order processors based on FeS2. The simulator can run unmodified Debian Linux and workloads in a virtual machine. • 2008 to 2010: Led the effort of building a 20-node FPGA-based full-system emulator comprising Intel MIC Knights Ferry cores on a 4x5 mesh/torus-based interconnect and demoed the emulator at 2010 Intel Developer Forum in San Francisco. The emulator ran a version of Linux and several visual computing related workloads. Also involved in the discussion which finally led to the memory ordering spec in x86 Software Developer’s Manual, volume 3. • 2005 to 2008: Responsible for the cache coherence protocol chapter of Intel QuickPath Interconnect specification. Revamped the chapter by introducing a table-based
  • 2. specification methodology that has since been adopted by other projects at Intel. Responsibilities included the specification, verification, and evolution of the protocol spec based on inputs from both internal and external customers, and the generation and maintenance of validation collaterals (such as executable reference models). • 2000 to 2005: Worked with product design teams on validating RTL implementation against protocol specifications by using both simulation and formal techniques. Developed and verified several cache coherence and other protocols which were not productized. Analyzed several error correction or detection codes and wrote an internal tutorial on CRC (cyclic redundancy check). • 1997 to 2000: Worked in the formal verification team of the Merced processor design project and used both formal verification and simulation techniques to find bugs in the RTL of a processor front-end unit and the bus cluster. Wrote simulation coverage monitors. Fujitsu Labs of America • 1995 to 1997: Designed an Esterel-like synchronous language based on interval temporal logic and developed a translation from this language to synchronous circuits. Education University of California, Los Angeles - Los Angeles, CA Ph.D. and M.S. in Computer Science National Taiwan University - Taipei, Taiwan B.S. in Electrical Engineering Online Courses • Coursera, Cryptography I, taught by Dan Boneh of Stanford University, Sep 2014 Statement of Accomplishment (Grade: 100% with Distinction) • Coursera, GPS: An Introduction to Satellite Navigation, taught by Per Enge and Frank van Diggelen of Stanford University, Dec 2014 Completed, Statement of Accomplishment pending Patents: https://sites.google.com/site/chingtsunchou/patents Publications: https://sites.google.com/site/chingtsunchou/publications Google Scholar Citation: http://scholar.google.com/citations?hl=en&user=ufGYoL0AAAAJ Award: 2005 Mahboob Khan Outstanding Mentor Awards from SRC (Silicon Research Corporation. Miscellaneous • Citizenship: U.S.A. • Erdös Number = 2 (http://www.oakland.edu/enp/)