The document summarizes an ARM technology update presentation. It introduced the new Cortex-A7 processor, which is aimed at highly efficient mobile workloads. It also described ARM's big.LITTLE processing approach, which uses more powerful and efficient cores together for optimal performance and battery life. Finally, it provided an overview of the new 64-bit ARMv8-A architecture, including its exception model and support for both 32-bit and 64-bit execution states.
2. Agenda
ARMv7-A update
Cortex-A7 announcement
Energy efficient processing
big-LITTLE: Cortex-A15 & Cortex-A7
Eco-system development
The architecture roadmap: ARMv7 => ARMv8
ARMv8-A announcement at TechCon 2011
3. ARM Cortex-A15 Momentum
Expanding list of ARM Partners with
designs in progress
…and 5 other ARM partners
Products expected in 2012
4. Introducing the Cortex-A7
A highly efficient core for future smartphones
Entry-level, some mainstream workloads
...and more
Redefines mobile computing
big.LITTLE processing model
Power
Performance
Cortex-A15
Cortex-A7
Cortex-A7 is ~1/6th the power,
but half the performance, at the
nominal operating point
Highest Cortex-A15
Operating Point
Highest Cortex-A7 Operating Point
Lowest Cortex-A15 Operating Point
Lowest Cortex-A7 Operating Point
Overdrive
Condition
Full backward compatibility
with Cortex-A processors
Feature set and software
compliant with Cortex-A15
Virtualization
Large Address Extensions
Scalable and Extensible
Multi-processor
System Coherency
Small
<0.5mm2 in 28nm process
ARM Cortex-A7
RTL available Now
5. Cortex-A15/7 big.LITTLE Processing
Cortex-A15
MPCore
L2 Cache
CPU
Cortex-A7
MPCore
L2 Cache
CCI-400 Coherent Interconnect
CPU
CPU CPU
Interrupt Control
Uses the right processor for the right job
Up to 70% energy savings on common workloads
Flexible and transparent to apps – importance of
seamless software handover
big
“Demanding tasks”
LITTLE
“Always on, always
connected tasks”
6. Performance and Energy-Efficiency
Simple, in-order, 8 stage pipeline
Performance better than today’s
mainstream, high-volume smartphones
Most energy-efficient applications processor from ARM
Complex, out-of-order, multi-issue pipeline
Up to 5x the performance of today’s
mainstream, high-volume smartphones
Highest performance in mobile power envelope
Cortex-A7
Cortex-A15
LITTLEbig
Q
u
e
u
e
I
s
s
u
e
I
n
t
e
g
e
r
7. big.LITTLE Cluster Migration Mechanics
Migration Stimulus Received
Save State
Normal Operation
Snooping Allowed
Outbound Processor (s): Cluster B
Cache Invalidate
Ready for migration
Switch State (Snoop Outbound Processor)
Inbound Processor(s): Cluster A
Outbound Processor OFF
Stimulus from OS/Virtualizer
via system firmware interface
Enable Snooping
Restore State
Normal Operation
Power Down
Power On & Reset
Disable Snooping
Clean Cache
Less than 100-cycles
Less than 20 micro-seconds
This is the “critical period”
where no work is being done on
either cluster
Cycle count is OS
dependent
8. Leading Software Ecosystem
Broad support for Cortex-A processors
100,000s of apps already optimized
Increasing ARM focus on the platform
1TB of physical address space
(Cortex-A7/A15 systems) meets a
wide spectrum of developer needs
a vehicle for software development
and sharing
Linaro key to Linux and other open-source
software and tools deployment Virtualization
and
Firmware
OS
Power Management Software
Applications and Middleware
Many ARMv7-A software developments
logically extend into ARMv8-A
9. Focus for ARM system and software development
Cortex-A15 cluster
Cortex-A7 cluster
Mali graphics support + Memory, IO, debug etc...
Increasing use of “models-first”: processor, memory & IO
Cortex-A15/A7/MALI platform
CPU 0
L2Cache
Cortex-A15 Cluster
LPDDR2/DDR3
Controller
DMC-400
System Power
Debug & Trace
2012 Compute Subsystem
AMBA Extensions
Interface (Slave)
AMBA Extensions
Interface (Master)
JTAG &
Trace
PMIC/
APB Bus
CPU 2
CPU 1 CPU 3
CPU 0
L2Cache
Cortex-A7 Cluster
CPU 2
CPU 1 CPU 3
Shader
Core
0
Mali T600 series GPU
Shader
Core
1
Shader
Core
2
Shader
Core
3
Cache Coherent Interconnect (CCI-400)
DDR PHY or DDR Memory
NIC 400
CoreSight
Resources
Mgt
SMMU
L2Cache
NIC 400
On-Chip
Memories
(RAM, ROM)
Base
Peripheral
11. What is ARMv8?
Next version of the ARMv8 architecture
First release covers the Applications profile only: ARMv8-A
Addition of a 64-bit operating capability
Introduction of new 64-bit execution state – AArch64
Maintain low power heritage – critique features against PPA* impact
ARMv7-A compatibility a critical consideration – AArch32
Interprocessing: defined relationship between 32- and 64-bit
execution
Maintain ARMv7-A (AArch32) momentum alongside AArch64
Strong compatibility plus ongoing evolution
*PPA: Power Performance Area
12. ARMv8-A – Context
• ARMv8
• A-profile only
(at this time)
• 64-bit architecture
support
14. Exception model overview
EL2
AArch32 AArch64
EL0
EL1
User
IF EL3 is 64-bit
Svc Abt Und
FIQ IRQ Sys
Hyp
User
Svc Abt Und
FIQ IRQ Sys
EL3
EL0
EL1h EL1t
EL3h EL3t
EL2h EL2t
SecureNon-secure SecureNon-secure
EL0
EL1h EL1t
„h‟andler &
„t‟hread
stack options
Svc Abt Und
FIQ IRQ Sys
Mon
IF EL3 is 32-bit
ARMv7-A
compatibility
Interprocessing:
• EL3: Secure Monitor => EL2: Hypervisor) => EL1: OS = EL0: Application
• AArch64 → AArch32 transition can occur on a transition down the hierarchy (EL3 → EL0)
• AArch32 → AArch64 transition can occur on a transition up the hierarchy (EL0 → EL3)
16. Summary
Cortex-A7 a highly efficient application processor
Cortex-A7 enables big.LITTLE Processing to
expand performance and battery-life
Seamless and transparent to application software
ARM increasing its platform software investments
A catalyst for many activities
The ARM architecture roadmap is now clearer
ARMv8-A architecture development is well advanced
(Specification release expected 2H-2012)