IRJET- Comparison of Power Dissipation in Inverter using SVL Techniques
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This document compares the power dissipation of different inverter circuit designs including static CMOS, domino, and domino with self-controllable voltage level (SVL) techniques. It finds that an upper SVL domino circuit has the lowest power consumption of 25.167 μW, which is 35.88% less than a static CMOS inverter. SVL techniques like upper and lower SVL help reduce leakage power by increasing threshold voltage. Simulation results in a 90nm technology show that an upper SVL domino inverter has lower power dissipation and propagation delay compared to other designs.
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![International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056
Volume: 05 Issue: 11 | Nov 2018 www.irjet.net p-ISSN: 2395-0072
© 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 888
Comparison of Power Dissipation in inverter using SVL Techniques
K. Kalai Selvi
Assistant Professor, Dept. of Electronics & Communication Engineering, Government College of
Engineering, Tirunelveli, India
---------------------------------------------------------------------***----------------------------------------------------------------------
Abstract - As technology scales the sizeofchip, leakagepower
has become a important component in chip design. Leakage
power isan essentialparameter to be taken into accountwhile
designinglowpowerdevices.Largeamountofleakagepowerisan
serious&undesirablefactorinportableelectronicsdevices.High
power consumption raises the cost and also reduces the
battery life of the devices. So it is essential to reduce the
dynamic as well as the static power consumption. Increasing
the threshold voltage reduces the leakage powerofthecircuit.
Low energy consumption in devices requires very low power
circuits. This paper compares the inverter circuits i.e static
CMOS inverter & Domino inverter with Upper & lower Self
controllable Voltage Level (SVL). Power Consumption & power
Dissipation of Upper SVL Domino circuit is found to be less . As power
dissipationisreduced,consequentlytheremustbeareductioninleakage
power. All the simulations have been carried out in Microwind
tool at 90 nm technology ,Vdd Supply of 1.2 volt is given , input
sequence used is 01010.The other name of Self controllable
VoltageLevel is Adaptive voltage level circuit (AVL).
Key Words: Static CMOS, USVL (upper selfcontrollable
voltage level) ,LSVL (lower self controllable voltage level),
Leakage current, Power dissipation.
1. INTRODUCTION
The latest trends in VLSI technology needs a reduction in
power supply voltage (Vdd) to reduce dynamic power in
deep sub-micron (DSM) regimes. However, a reduction in
Vdd decreases the threshold voltage (Vth).Thisreductionin
Vth causes the leakage currents to increase exponentially
and they become a important contributor to total power
dissipation in VLSI chips. The subthreshold leakage current
Ileak is given by the expression
Ileak = I0 exp[(Vgs – Vth)/nVT] --- (1)
where I0 = μ0 Cox (W/L) V2 e1.8,
Cox = gate oxide capacitance, (W/L) = widthtolengthratio of
the leaking MOS transistor., μ0 = zero biasmobility,Vgs=gate
to source voltage, VT = thermal voltage which is about 26mV
at temperature T= 300K and n is the subthreshold swing
coefficient given by 1 +(Cd/Cox) where Cd is the depletion
layer capacitance of the source/drain junction.Theequation
(1) says that the leakage current is exponentially
proportional to (Vgs -Vth), Which implies leakage can be
reduced by increasing Vth or reducing Vgs. Domino logic is
one of the effective circuit configurations for implementing
high speed logic designs. Domino circuits provide the
advantages of faster transition and glitch-free operation.
1.1 DOMINO LOGIC
Dynamic circuits such as domino logic circuits are used in
high performance microprocessorsforobtaininghighspeeds
that are not possible with static CMOS circuits . Their high
speed is due to reduced input capacitance, small switching
thresholds and circuit implementations that typically use
fewer levels of logic due to the usage of efficient and wide
complex logic gates. But the penalty to be paid for speed
improvement is the increased powerdissipation,mainlydue
to the necessary clocking and increased noise sensitivity.
Hence, this imposes the challenges in the design of dynamic
circuits.
1.2. DOMINO INVERTER
Domino style incorporates clk inputs to all gates.The
operation of these gates is divided into 2 phases. The phases
are precharge & evaluation . In the precharge phase gate
outputs are charged to high level voltage because PMOS
transistors are controlled by clock input which in this phase
is low .In the evaluate phase, the outputs of the gate can
conditionally change to low voltage level. The logic of the
gate is implemented only with NMOS transistors those
transistors dictate if the outputs will be connectedtothe low
voltage level to be dischargedornot.HereDominoInverteris
implemented in 90 nm technology using Microwind. When
clkdata is low ,in precharge state Pmos1 conducts output is
driven depending on clk data i.epmos2conductssooutputis
charged to Vdd, in evaluate phase clock1 is high so nmos2
conducts & nmos1 doesn’t conduct so out1 retains the
charge. When clkdata is high nmos1 conducts ,in precharge
phase pmos1 conducts, so output is reduced as it discharges
since pmos2 is off & in evaluate phase nmos2 conducts so
output is pulled down to 0.The schematic diagram is shown
in fig 2 .Vdd Supply of 1.2 volt is given, input sequence is
01010.
Figure -1: A Domino Logic inverter Circuit](https://cdn.statically.io/img/image.slidesharecdn.com/irjet-v5i11172-181205060800/85/IRJET-Comparison-of-Power-Dissipation-in-Inverter-using-SVL-Techniques-1-320.jpg)
IRJET- Comparison of Power Dissipation in Inverter using SVL Techniques
- 1. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 11 | Nov 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 888 Comparison of Power Dissipation in inverter using SVL Techniques K. Kalai Selvi Assistant Professor, Dept. of Electronics & Communication Engineering, Government College of Engineering, Tirunelveli, India ---------------------------------------------------------------------***---------------------------------------------------------------------- Abstract - As technology scales the sizeofchip, leakagepower has become a important component in chip design. Leakage power isan essentialparameter to be taken into accountwhile designinglowpowerdevices.Largeamountofleakagepowerisan serious&undesirablefactorinportableelectronicsdevices.High power consumption raises the cost and also reduces the battery life of the devices. So it is essential to reduce the dynamic as well as the static power consumption. Increasing the threshold voltage reduces the leakage powerofthecircuit. Low energy consumption in devices requires very low power circuits. This paper compares the inverter circuits i.e static CMOS inverter & Domino inverter with Upper & lower Self controllable Voltage Level (SVL). Power Consumption & power Dissipation of Upper SVL Domino circuit is found to be less . As power dissipationisreduced,consequentlytheremustbeareductioninleakage power. All the simulations have been carried out in Microwind tool at 90 nm technology ,Vdd Supply of 1.2 volt is given , input sequence used is 01010.The other name of Self controllable VoltageLevel is Adaptive voltage level circuit (AVL). Key Words: Static CMOS, USVL (upper selfcontrollable voltage level) ,LSVL (lower self controllable voltage level), Leakage current, Power dissipation. 1. INTRODUCTION The latest trends in VLSI technology needs a reduction in power supply voltage (Vdd) to reduce dynamic power in deep sub-micron (DSM) regimes. However, a reduction in Vdd decreases the threshold voltage (Vth).Thisreductionin Vth causes the leakage currents to increase exponentially and they become a important contributor to total power dissipation in VLSI chips. The subthreshold leakage current Ileak is given by the expression Ileak = I0 exp[(Vgs – Vth)/nVT] --- (1) where I0 = μ0 Cox (W/L) V2 e1.8, Cox = gate oxide capacitance, (W/L) = widthtolengthratio of the leaking MOS transistor., μ0 = zero biasmobility,Vgs=gate to source voltage, VT = thermal voltage which is about 26mV at temperature T= 300K and n is the subthreshold swing coefficient given by 1 +(Cd/Cox) where Cd is the depletion layer capacitance of the source/drain junction.Theequation (1) says that the leakage current is exponentially proportional to (Vgs -Vth), Which implies leakage can be reduced by increasing Vth or reducing Vgs. Domino logic is one of the effective circuit configurations for implementing high speed logic designs. Domino circuits provide the advantages of faster transition and glitch-free operation. 1.1 DOMINO LOGIC Dynamic circuits such as domino logic circuits are used in high performance microprocessorsforobtaininghighspeeds that are not possible with static CMOS circuits . Their high speed is due to reduced input capacitance, small switching thresholds and circuit implementations that typically use fewer levels of logic due to the usage of efficient and wide complex logic gates. But the penalty to be paid for speed improvement is the increased powerdissipation,mainlydue to the necessary clocking and increased noise sensitivity. Hence, this imposes the challenges in the design of dynamic circuits. 1.2. DOMINO INVERTER Domino style incorporates clk inputs to all gates.The operation of these gates is divided into 2 phases. The phases are precharge & evaluation . In the precharge phase gate outputs are charged to high level voltage because PMOS transistors are controlled by clock input which in this phase is low .In the evaluate phase, the outputs of the gate can conditionally change to low voltage level. The logic of the gate is implemented only with NMOS transistors those transistors dictate if the outputs will be connectedtothe low voltage level to be dischargedornot.HereDominoInverteris implemented in 90 nm technology using Microwind. When clkdata is low ,in precharge state Pmos1 conducts output is driven depending on clk data i.epmos2conductssooutputis charged to Vdd, in evaluate phase clock1 is high so nmos2 conducts & nmos1 doesn’t conduct so out1 retains the charge. When clkdata is high nmos1 conducts ,in precharge phase pmos1 conducts, so output is reduced as it discharges since pmos2 is off & in evaluate phase nmos2 conducts so output is pulled down to 0.The schematic diagram is shown in fig 2 .Vdd Supply of 1.2 volt is given, input sequence is 01010. Figure -1: A Domino Logic inverter Circuit
- 2. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 11 | Nov 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 889 2. SELF CONTROLLABLE VOLTAGE LEVEL SVL standsforSelf controllableVoltageLevel.Selfcontrollable voltage level (SVL) is technique for leakage reductionwithin the device. SVL is a technique which can be set either at the top of the load circuit, or bottom of the load . Upper self controllable voltage level (USVL) technique is applied to reduce the supply voltage and Lower self controllable voltage level (LSVL) system isutilizedtoboostuptheground node voltage. 2.1 LOWER SELF CONTROLLABLE VOLTAGE LEVEL (LSVL) An LSVL circuit in general, consists of a single NMOS switch and m weakly connected nMOS switches connectedinseries which increases the source voltage appearing across the load circuit in active mode. Here m=2 is considered. A negative control signal (clk2)turnsonpmos_3&pmos_2 and turns off nmos_1. so that VS is supplied to the stand-by inverter through 2 p-SWs.The on-NMOS switch connectsthe load circuit and Vss in the sleep mode on request whereas the weakly-on PMOS transistors connect the loadcircuitand Vss in the active mode. Source voltage (VS) is increased by mv, so the substrate bias (i.e., back-gate bias) (Vsub), expressed by Vsub = – mv ----(2) Vs=Vss+2v ----(3) Figure -2:Lower Self controllable Voltage Level Circuit Figure -3:Lower Self controllable Voltage Level Circuit with static cmos inverter as load 2.2 UPPER SELF CONTROLLABLE VOLTAGE LEVEL Figure- 4: Upper Self controllable Voltage level
- 3. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 11 | Nov 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 890 Figure-5: Upper Self controllable Voltage level with static cmos inverter as load An USVL circuit, in general, consists of a single PMOS switch and m weakly connected nMOS switches connected in series.Here m=2 is considered. Whengatevoltageofstandby inverter is “0” ,pmos2-2 is turned on & nmos3_1 is turned off. When clockavl turns on nmos1_5 , nmos2_4 & turns off pmos1_3, Vdd is supplied to inverter through 2 nmos. Now, the drain volltage of off nmos is Vdsn = Vdc – 2v -----(4) v is voltage drop in single nmos.Hence, Vdsn is reduced which in turn increases the barrier height of the off-Nmos. Therefore Drain Induced Barrier Lowering (DIBL) effect is reduced and therefore the threshold voltage of the nMOS transistor is increased. This results in a decrease in sub- threshold leakage current of the nMOS transistor in the load circuit. 2.3 LOWER SELF VOLTAGE LEVEL CIRCUIT WITH DOMINO INVERTER AS LOAD Figure -6: Lower Adaptive Voltage Level Circuit with Domino Inverter as load Figure -7: Voltage waveforms & power consumption Lower Adaptive Voltage Level Circuit with Domino Inverter as load
- 4. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 11 | Nov 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 891 Figure -8: Power dissipation of Lower Adaptive Voltage Level Circuit with Domino Inverter as load 2.4 UPPER ADAPTIVE VOLTAGE LEVEL CIRCUIT WITH DOMINO INVERTER AS LOAD Figure -9: Upper Adaptive Voltage Level Circuit with Domino Inverter as load Figure -10: Voltage waveforms & power consumption Upper Adaptive Voltage Level Circuit with Domino Inverter as load Figure -11: Power dissipation of Upper Adaptive Voltage Level Circuit with Domino Inverter as load TABLE-1: SIMULATION RESULTS 3. CONCLUSION The simulation results reveal that Upper SVL with Domino inverter has less power consumption of 25.167 μW which is 35.88 % less than Static CMOS inverter.Power Dissipation is 0.025mW in Upper SVL with Domino inverter which is 35% less than Static CMOS inverter.PropagationDelayisalsoless i.e 700 ps.Domino inverter with USVL is better in performance than with LSVL . So it can be concluded that USVL is better choice. REFERENCES [1] Pushpa Saini,Rajesh Mehra Leakage Power Reduction in CMOS VLSI Circuits, International Journal of Computer Applications (0975 – 8887) Volume 55– No.8, October2012. [2] Rita Fariya ,T.Sai Baba, D.Lakshmaiah, Deign of Low power Domino Logic Circuits, International Journal of Technology and Engineering Science [IJTES]TM Volume 3[12], pp: 5156-5160, December 2015 [3] Ms.Amrita Pahadia #1, Dr. Uma Rathore Bhatt Layout Design, Analysis and Implementation of Combinational and
- 5. International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 05 Issue: 11 | Nov 2018 www.irjet.net p-ISSN: 2395-0072 © 2018, IRJET | Impact Factor value: 7.211 | ISO 9001:2008 Certified Journal | Page 892 Sequential Circuits using Microwind , SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – volume2 Issue 2 May to Aug 2015 [4] Ankita Sharma, Divyanshu Rao, Ravi Mohan, Design and Implementation of Domino Logic Circuit in CMOS Journal of Network Communications and Emerging Technologies (JNCET) www.jncet.org Volume 6, Issue 12, December (2016) [5] Pushpa Raikwal, V. Neema, S.Katiyal LOWPOWERWITH IMPROVEDNOISEMARGIN FOR DOMINOCMOSNANDGATE International Journal Of Computational Engineering Research / ISSN: 2250–3005 [6] Domino Logic Circuit with Reduced Leakage and Improved Noise Margin, H. Mangalam* and K. Gunavathi ,International Journal of Applied Engineering ResearchISSN 0973-4562 Volume 2, Number 4 (2007), pp. 585–593 [7] K. Kalai Selvi , Enhancement of Back Gate Bias to Reduce Power Dissipation in Domino Inverter by Lower Adaptive Voltage Level Circuit ,Journal of Network Communications and Emerging Technologies (JNCET) Volume 8, Issue 10, October (2018) BIOGRAPHY K. Kalai Selvi completed M.E in Optical Communication at Alagappa Chettiar College of Engineering & Technology, Anna University. Working as Assistant Professor in Government College of Engineering ,Tirunelveli, Tamil Nadu. Has 12 years of teaching experience.