This document proposes a low-power full adder array-based multiplier circuit design using domino logic. It is based on the Wallace tree technique. The proposed circuit uses a clocked architecture that results in lower power dissipation and improved power-delay product compared to traditional designs. As a proof of concept, the authors implemented an 8x8 bit multiplier using multiple 4x4 bit multiplier blocks. Simulation results show the 8x8 multiplier design has an average power of 0.11108 microwatts when implemented using a 0.5um CMOS process at 5V supply voltage.