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Every electronics engeneer knows that connecting more chips on the same line increases its capasistence and, thus, degrades the frequency. So, memory speed must be dependent on the number of chips in the channel. How in this case the DDR memory manufacturers manage to label their devices as DDR3-1333 MHz for instance without this information? Is there a limit of chips per channel or one module per channel is assumed?

Apart from that, what if there is capacity imbalance in multicahhel architecture? Here is a recommendation from my MB manufacturer, X58A-UD3R, to use 4 modules for 3-channel mode enter image description here Can I have 4GB+2GB+2GB (assuming the timings are identical)? What are performance Implications? The Intel controller says that interleaving mode is needed to make gain of 3 channels. What will happen to the interleaving when there is such capacity imbalance?

What if modules of different timings are combined? Should I choose the worst common denominator?

In other words, I want to know what are DIMM specifications depending on the environment? How are the DIMM specifications related with the environment it is supposed to work?

Originally posted in http://www.tomshardware.co.uk/answers/id-1651405/miltiple-sticks-single-channel.html

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  • The label on a memory module is simply the maximum speed at which it is capable of operating. It is not a guarantee that it will operate at that speed in any particular system.
    – Dave Tweed
    Commented Apr 14, 2013 at 14:16
  • thanks, this is interesting but incomplete. I want to know more exactly: how the maximum speed is affected when I combine memories?
    – Val
    Commented Apr 14, 2013 at 14:41
  • That depends on your memory controller and the number of memory ranks on the DIMM(s). In the case of most regular PCs (with ranks 2 DIMMs) max speed does decrease when you add a second pair (or in the case of Nehalens or some Xeons, a a second triplet/second quad) of DIMMs.
    – Hennes
    Commented Apr 14, 2013 at 16:07
  • @Hennes, how is it possible? The DIMM sticks are it the same position as the controller. They must drive more capacity when connected to the other DIMM chips. How do you know that it is controller dependent? Why SDRAM standard prescirbes the RAM chips to support other chips in the channel but SDRAM controller may violate this requirement? How do I know which category my controller belongs?
    – Val
    Commented Apr 14, 2013 at 16:25
  • Some MB manufacturers will actually list memory modules that have been tested to work with that motherboard. So no guessing is needed by the end-user.
    – sawdust
    Commented Apr 14, 2013 at 22:27

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I have discovered that there are ganged and unganged multichannels. In the Henessy & Patterson we read (where do they take this info from?):

The i7 has three 64-bit memory channels that can act as one 192-bit channel, since there is only one memory controller and the same address is sent on both channels

That is, it seems that Intel Core i7 processors are "ganged". So, I will have speedup only when 3 matched dimms are read at a time. AMD meantime provides truly independent channels, ie.e unganged ones, which give more combination freedom and performance. Random Access Memory can be accessed more randomly with AMD processors!

Nevertheless, nothing says that controller stops accessing 3 existing parallel sticks in parallel 3-channel mode if I add one more DIMM into the first channel.

edit I have just added one more DIMM stick, as the diagramm shows and both CPU-Z and BIOS show that I still have 3 channels. They do not tell that controller operates in 1- or 2-channel mode. The only problem is the reduced timing 7-7-7 to 8-8-8 in the first channel. But it is electrical capacitance issue, not memory access schema, which seems to stay the same.

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