I have the following hardware:
- P35-DS3L supporting FSB 333/266/200 Mhz, quad-pumped. Four dual-channel slots.
- E2180 currently @ 2.00Ghz (200.00x10)
I plan to raise the FSB to 266.66.
This is my visualization of the block diagram:
------------------------
--> |[64-bit]2x SDRAM DIMMs|
----- ----------------------------------------------------- / ------------------------
|CPU| <-- FSB [64-bit]--> |Northbridge (Intel P35): Memory Controller[128-bit]| <-- Memory I/O Bus ---
----- ----------------------------------------------------- \ ------------------------
--> |[64-bit]2x SDRAM DIMMs|
------------------------
Matching Memory Using Bandwidth
I was having trouble accounting for the mismatch between the FSB and Memory I/O Bus frequencies, until I found this elegant answer suggesting to match bandwidth instead of frequency.
bandwidth = [bus clock] * [data rate] * [data width] / 8
The bandwidth on the (quad-pumped) FSB side:
[email protected] = 200.00 * 4 (for quad-pumped) * 64 / 8 = 6400 MB/s
[email protected] = 266.66 * 4 (for quad-pumped) * 64 / 8 = 8533 MB/s
Now to match this bandwidth on the memory side for a single DIMM:
[email protected] = DDR2-800 : 400.00 * 2 * 64 / 8 = 6400 MB/s
[email protected] = DDR2-1066 : 533.33 * 2 * 64 / 8 = 8533 MB/s
Now to match this bandwidth on the memory side for dual-channel:
[email protected] = DDR2-400 : 200.00 * 2 * 64 / 8 * 2 (for dual channel) = 6400 MB/s
[email protected] = DDR2-533 : 266.66 * 2 * 64 / 8 * 2 (for dual channel) = 8533 MB/s
Now however there is no guarantee that the memory requests will be balanced equally between both channels. Each request to the memory controller in a dual-channel layout may have a benefit ranging from [1..2]. For example, given an [email protected] and two DIMMs of DDR2-400 in separate channels, if the CPU requests 64 bits of data solely from channel 1 (none from channel 2), then that particular request will need by completed over two transfers.
Therefore, my conclusion is to purchase two DIMMs of DDR2-1066 SDRAM in anticipation of overclocking the FSB to 266.66MHz. Is this correct?
Of course, given 50/50 odds (ie a linear efficacy of the dual channels), faster RAM provides diminishing returns, especially compared to $$. And perhaps the CPU is always able to batch memory requests to always utilize most efficiently the dual channels, in which case I should instead purchase two DIMMs of DDR2-533 in anticipation of overclocking the FSB to 266.66MHz? Or is this correct?
Matching Memory Using Frequency
How would I perform the same calculation by matching frequencies instead of bandwidth? The wikipedia article on memory dividers provides an example I don't understand.
The memory divider denotes the ratio between the FSB frequency and the Memory I/O Bus frequency. If, as per the article, the FSB operates at 200MHz with a memory divider of 1:1, then the Memory I/O Bus also operates at 200MHz. The article then claims this is compatible with DDR2-800 SDRAM. Why? DDR2-800 SDRAM operates at 400MHz, not 200MHz.
My working assumption is that the memory divider only denotes the ratio of effective (not actual) frequencies. For example, quad-pumped FSB of 200MHz has an effective data transfer rate of 800Mhz. Dual-data rate operating at 400MHz has an effective data transfer rate of also 800Mhz. This implies the memory I/O Bus actually runs at 400MHz, a fact glossed over in the memory divider ratio. Is this correct?
From what I gather, the RAM prefetch buffer is also completely immaterial to this discussion. The prefetch buffer is completely internal to the DIMMs: it allows the internal memory clock to run at half the Memory I/O Bus clock without a drop in bandwidth.
