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Matthew Taylor's user avatar
Matthew Taylor's user avatar
Matthew Taylor
  • Member for 8 years, 5 months
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Trainer for digital design, VHDL, Verilog, SystemVerilog and UVM.

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Top posts
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20
Difference between unsigned and std_logic_vector
Jun 15, 2017
15
Verilog signed multiplication: Multiplying numbers of different sizes?
Jun 20, 2016
13
urandom_range(), urandom(), random() in verilog
Apr 19, 2016
11
what are the uses of case 'inside's in verilog ? is it synthesizable?
Aug 13, 2019
10
Large Array Initialization to 0
Jun 1, 2017
9
Prefered syntax for verilog module declaration
Aug 24, 2016
8
System Verilog - case with or
Jan 5, 2017
8
What is "net" in HDL synthesis
Mar 3, 2017
8
I'm getting this error for my verilog code, "Illegal operation for constant expression"
Feb 17, 2020
8
VHDL Error(10482) object std_logic_vector is used but not declared
May 1, 2019
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Sympathy for a tag synonym request required
11
Posting questions and answers from my blog
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6
What's the word for not wanting to repeat a semantic atom?