gitignore for VHDL project

Question

I'm beginning to work on an already started project in VHDL: many simulations and compiling have already been done on this project.

I decided to use Git to be able to work from many computers but I still have to push the files to the repository. Since the project is full of .exe and other compile output files it takes forever to upload (I know Git is very in efficient in the conversion to binary files).

However it's the first time I work with VHDL so I can't distinguish between source files and simulation/compile outputs.

I'm working on a Xilinx Spartan-6, with the Xilinx ISE (can't tell if it's the WebPack or the Design Suite, but I'd say the WebPack)

What file extensions should I include in the .gitignore?

Answer 1

This depends heavily on your simulator/toolchain. I know Riviera-PRO uses .asbd, .awc, .lib, .mgf, .data, .index and some extension-less files for simulation. I think GHDL might use at least .exe files, but I've never used it. Altera and Xilix implementation toolchains also use different (and many) file extensions for synthesis. You might be better off keeping separate source and simulation/compilation directories and only use revision control on your source directory (and maybe a folder for release binaries if you need to).

File extensions you want is easier to define. VHDL sources are .vhd or .vhdl files. Verilog uses .v and .vh.

You will also need your timing constraints (and maybe build scripts if you don't do a project flow - they often don't have file extensions though) to do a build. Xilinx ISE timing constraints are .xcf and .ucf files .