How to prevent GNU Make from interpreting a string?

Question

As I mentioned in this post, I generally upgrade my git submodules recursively as follows:

git submodule foreach 'git fetch origin; git checkout $(git rev-parse --abbrev-ref HEAD); git reset --hard origin/$(git rev-parse --abbrev-ref HEAD); git submodule update --recursive; git clean -dfx'

This command works perfectly when invoked from a terminal. Now I have trouble to embed it in GNU make as in the upgrade target of this Makefile. If I simply copy paste the command:

upgrade:
   git submodule foreach 'git fetch origin; git checkout $(git rev-parse --abbrev-ref HEAD); git reset --hard origin/$(git rev-parse --abbrev-ref HEAD); git submodule update --recursive; git clean -dfx'

it does not work: GNU make tries to evaluate / interpret the $(git ...) section despite the presence of simple quotes. I tried several attempts without success so far ($$\(git ...), defining a verbatim command as explained here etc.).

Do you have a suggestion?

Answer 1

The only character that is special to make in a recipe is $ (and backslash/newline combinations, but only backslashes before newlines, nowhere else). Every other character is ignored and passed through to the command.

And, the only way to quote the $ is by doubling it, to $$.

So, to quote $(git rev-parse ...) you just write $$(git rev-parse ...). No need for backslashes etc. Just take the shell command and every $ you want to use literally, everywhere in the string, ignoring ALL types of shell quoting, make it into $$.