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Is there a notion of fault-tolerance of logical gates that also accounts for the underlying hardware? If so, how is this notion / term called?

An example:

A possible choice of logical basis states in the $[[4, 2, 2]]$ code would be:

$$|00\rangle_L = \frac{1}{\sqrt 2}(|0000\rangle + |1111\rangle $$ $$|01\rangle_L = \frac{1}{\sqrt 2}(|0110\rangle + |1001\rangle $$ $$|10\rangle_L = \frac{1}{\sqrt 2}(|0101\rangle + |1010\rangle $$ $$|11\rangle_L = \frac{1}{\sqrt 2}(|0011\rangle + |1100\rangle $$

The logical CNOT (with the first qubit being the control qubit) can be realized by a SWAP on physical qubits 2 and 3.

Now, I was wondering if this can be considered a fault-tolerant operation.

This depends on how the SWAP gate is realized on the physical level, right? As I understand it, superconducting technology realizes this by a series of physical CNOTs. While with neutral atoms or ions, you could just move the physical qubits around in physical space and hence swap them.

I conclude that the superconducting realization would not be fault-tolerant as a single faulty operation could result in more than one fault per encoded block. While the neutral atoms realization would be fault-tolerant assuming the physical SWAP cannot not cause errors.

Is there a term for this "hardware-dependent" notion of fault-tolerant logical gates?

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  • $\begingroup$ I have two remarks. 1) You could in either case choose not to swap the qubits, but to modify subsequent gates accordingly (this might require increased connectivity on the hardware) 2) You might be making an unstated assumption that physical swapping does not spread errors, which is not obvious to me not knowing implementation details. You might as well want to link fault tolerance to some error model and not necessarily to a specific hardware. $\endgroup$
    – AG47
    Commented May 23 at 13:48
  • $\begingroup$ Thanks for the remarks. About 2): I edited my question to explicitly state the assumption. About 1): depending on the subsequent gates, you might eventually be force to physically swap qubits due to the logical CNOT. If that is so, I would consider the CNOT to be non-fault-tolerant (if the physical swap is done via three physical CNOTs) $\endgroup$
    – qubitzer
    Commented May 23 at 14:36
  • $\begingroup$ In my understanding, fault tolerance is a high-level notion defined for logical operations on a class of quantum codes with increasing distance that is sufficient for error-corrected quantum computation to scale. This is to me conceptually far from the low-level considerations of the hardware, hence my point in talking about error model instead. $\endgroup$
    – AG47
    Commented May 23 at 15:16
  • $\begingroup$ Also, it is more a question of the physical $SWAP$ not spreading errors than causing them I think. Causing a single non-correlated error is fine for fault tolerance. $\endgroup$
    – AG47
    Commented May 23 at 15:19
  • $\begingroup$ Yes, I used a common "working definition" of fault-tolerance that demands errors not to spread within an encoded block. A SWAP being implemented as 3 CNOTS would be an "error spreader", e.g. if the first CNOT causes a certain Pauli Error. $\endgroup$
    – qubitzer
    Commented May 24 at 7:36

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