Is the routing table a control plane concept or a data plane concept?

Question

I've always been told that the routing table is a control plane concept. You build this table, collect the routes, the way they were learned, their metrics, and so on.

You then use this information to build a more forwarding-suitable table, the forwarding information base (FIB) which is a CEF concept. This table is then what's actually used to perform route lookups and is optimized for forwarding data.

However, this doesn't work the same if CEF is disabled. If CEF is disabled, process-switching takes place. With process-switching, there is no FIB, so the device actually performs a route lookup in the routing table this time, right?

So with process-switching, doesn't this make the routing table also a part of the data plane?

Note: I understand that CEF should not be disabled, I just want to know this from a theoretical perspective.

Answer 1

The effective routing table or forwarding information base FIB is part of the data or forwarding plane.

The control plane keeps a more detailed routing information base RIB that is used for exchanging information with other routers over routing protocols and for creating the FIB.

CEF is an optimization technique by Cisco that maintains the basic premise above. It reduces the control plane's overhead.

Whether the data plane is implemented in hardware or in software doesn't really matter, it is (or should be) separated at least logically from the control plane.

Answer 2

In case CEF is disabled each packet will be processed in CPU and not by a dedicated hardware component optimized for super fast route lookups. Route lookup in software could be fast also - check out VPP(Vector Packet Processing).

In VPP, packets are grouped together into vectors, typically containing 256 packets each. This vector of packets is then processed together through a series of modular processing nodes represented as a graph. These nodes perform various operations on the entire vector of packets simultaneously, improving efficiency and reducing CPU overhead.