-
Notifications
You must be signed in to change notification settings - Fork 371
Issues: The-OpenROAD-Project/OpenLane
Magic DRC check reporting 0 errors in Openlane and MPW local ...
#2040
by ellen-wood
was closed Nov 11, 2023
Closed
2
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
[ERROR GRT-0118] Routing congestion too high.
question
The user needs help
waiting on op
Information has been requested from the Issue Author
#2130
opened Jun 24, 2024 by
Sanchit-Gupta10
Error: multi_corner.tcl line 43
waiting on op
Information has been requested from the Issue Author
#2123
opened May 20, 2024 by
fazliemre
Generating the PDN fails at the "Hierarchical chip design (with macros)" tutorial
bug
Something isn't working
documentation
Improvements or additions to documentation
#2121
opened May 7, 2024 by
kietuan
Clock Network Delay is 0.0 in timing reports after CTS
bug
Something isn't working
#2120
opened Apr 26, 2024 by
Jaswanth-Pappula
Enable rtl_macro_placer feature
enhancement
New feature or request
OpenLane 2
Scheduled for next gen OpenLane
#2117
opened Apr 12, 2024 by
vijayank88
ldpcEncDec Step 18 18-resizer_design.log failed
question
The user needs help
#2104
opened Mar 21, 2024 by
manish03
issues in using the floorplan core utilization command
question
The user needs help
waiting on op
Information has been requested from the Issue Author
#2101
opened Mar 11, 2024 by
Ashutosh-3107
unable to view the floorplan def files in klayout of oprn lane
bug
Something isn't working
Klayout
waiting on op
Information has been requested from the Issue Author
workaround
A workaround exists for this issue
#2095
opened Feb 26, 2024 by
Ashutosh-3107
Unbalanced buffer insertion on high fanout designs
question
The user needs help
#2090
opened Feb 6, 2024 by
Dolu1990
flow succeeds even if clock signal wire is unconnected / doesn't exist
Yosys
This issue is related to yosys
#2083
opened Jan 10, 2024 by
mattvenn
Getting -from and -to are no longer supported
OpenLane 2
Scheduled for next gen OpenLane
#2081
opened Jan 2, 2024 by
ShankarSNP
ERROR]: Synthesis failed. Signal not matching port size. Search for 'Resizing cell port'
waiting on op
Information has been requested from the Issue Author
#2078
opened Dec 28, 2023 by
alishan1213
Command 'make test' not working after installing OpenLane
bug
Something isn't working
#2064
opened Dec 11, 2023 by
srichandrasrii
[ERROR STA-0026] unterminated string constant
bug
Something isn't working
OpenROAD
An issue with an OpenROAD component
#2063
opened Dec 10, 2023 by
thesourcerer8
PDN pitch error
question
The user needs help
waiting on op
Information has been requested from the Issue Author
#2053
opened Nov 21, 2023 by
kirubakaran-g
CURRENT_ODB is unset
when follow Designing a chip with an OpenRAM (sky130)
bug
#2032
opened Oct 30, 2023 by
PeterBorisenko
Metal Spacing violation between interconnect and macro (sky130)
bug
Something isn't working
OpenROAD
An issue with an OpenROAD component
#2030
opened Oct 30, 2023 by
Dolu1990
Downloadable document
documentation
Improvements or additions to documentation
enhancement
New feature or request
#2016
opened Oct 11, 2023 by
alwinshaju08
Previous Next
ProTip!
Exclude everything labeled
bug
with -label:bug.