All Questions
Tagged with transceiver fpga
15
questions
1
vote
1
answer
128
views
Operating QSFP-28 at data rate other than 25Gbps per lane
We are designing a custom board for AD9082 and serdes of which are mapped to QSFP-28 port.This board will communicate with FPGA board using QSFP-28 module.
AD9082 and FPGA will linkup using JESD204C ...
- 41
1
vote
1
answer
845
views
Intra Pair Length Mismatch Tolerance For 12.5Gbps signals
I'm making a high-speed transceiver design and want some direction regarding layout of trace length from P to N. The speeds will be up to 12.5Gbps. I have been informed by a equalizer manufacturer ...
- 141
2
votes
1
answer
843
views
Do P/N matter for Diff Pair Clock Inputs to FPGA?
I have noticed on a schematic for an FMC card that the differential pairs of a differential LVDS oscillator do not match the corresponding FPGA transceiver reference clock pins. I.e. the P/N are ...
- 141
0
votes
1
answer
466
views
Data Oversampling Transceivers
I am trying to find more information about data oversampling for transceivers when grabbing/sending a lower speed signal. I am looking into building a fully compliant HDMI 1.4b fpga core, and have ...
- 141
0
votes
1
answer
166
views
Can transceiver replace SPI, I2C and other "normal" methods for high speed data transfer between FPGAs? If so, how? [closed]
SPI, I2C and UART are some well known serial methods for data transfer between devices on the same PCB. However, they all have a data rate bottleneck which is significantly lower than Multi Gigabit ...
- 12k
2
votes
1
answer
5k
views
Difference between PCS and PMA loopback in transceivers
Can someone let me know the difference between PCS and PMA loopback used in XILINX transceiver IBERT testing.
- 89
0
votes
2
answers
457
views
Gigabit transceiver with MHz reference clock
I've some experience with Xilinx FPGA generating 10Gb/s over SMA loopback with on-off keying modulation (what scope shows) to perform BER test but the documentation shows it uses a reference clock in ...
3
votes
2
answers
359
views
Data Transfer without Transceiver on FPGA
While going through the transceiver component on an FPGA, I realized that data transfer can take place without transceivers as well, although the speed would reduce or in other words, as tasks ...
- 31
1
vote
1
answer
855
views
10GBASE-R 64B/66B Encoding/Decoding Unusual Control Block Formats
I need to design a 64B/66B decoder on receiver side of the GTY transceiver. Currently, I get 2 bit header and corresponding 64 bit descrambled payload at positive edge of every other clock cycle. So ...
- 13
0
votes
1
answer
163
views
Generate high speed data using GTX transceiver of Kintex-7 FPGA board
I want to use Genesys-2 FPGA board as a BER tester for transceiver circuits. I am using IBERT IP core available in Vivado for it. Genesys-2 has an FMC connector to provide output for which I am using ...
- 15
0
votes
1
answer
107
views
How to model a physical channel using verilog?
I don't have access to high speed transceivers FPGA. So i wish to model the channel of high speed transceivers which is not error free so that i can test my codes if they are working fine or not.
Is ...
- 13
-1
votes
1
answer
36
views
wirelessHD using with FPGA
I going to make a system to transfer data between 2 FPGAs wirelessly with high rate.
I found that wirelessHD method can do this, now what is the required hardware to establish such system?
0
votes
3
answers
157
views
How can a transceiver pin be used if its clock is so much faster than the FPGA clock?
I'm trying to understand how a transceiver pin can actually operate at, say, 2.5GHz given that the clock speed of an FPGA is so much slower. In my understanding, to transmit data you need to ...
- 474
13
votes
1
answer
10k
views
Transceivers in the field of FPGAs: When and why will we use them?
I am recently getting myself into the field of FPGA design and development, and lately I've found myself hearing a lot about transceivers. I tried searching the net for some answers about these ...
- 231
1
vote
4
answers
2k
views
what is a transceiver reconfiguration controller on FPGA
I have come across this on an (Altera) FPGAs that make use of high speed protocols but don't know what it does.
- 12k