All Questions
Tagged with soc digital-logic
4
questions
2
votes
1
answer
841
views
Relationship between PSEL and PENABLE signals in the APB protocol
I would like some clarification on the relationship between the PSEL and PENABLE signals in the APB Protocol. The specification states:
The PENABLE signal is asserted the following clock after PSEL ...
- 41
0
votes
1
answer
86
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What happens when there are multiple Read requests to the same address in AXI3/4? Does RVALID assert each time?
Basically the title. I am trying to do a verification on an AXI4Lite protocol. If I try to send a read request to the same address multiple times the RVALID is not re-asserted. Correct data just ...
- 33
1
vote
2
answers
652
views
Techniques to develop software and hardware of a SoC in parallel
Hardware development takes a lot of time to develop. If a company is building a System-on-chip (SoC), the RTL model of the SoC is only available after the RTL integration is complete. This requires ...
- 2,331
0
votes
1
answer
372
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The datasheet says that USB operates on 1.8v instead of 3.3v, do I need some sort of logic level shifter in my circuit?
I'm trying to design a breakout board and connect the Google coral chip to my Toradex Colibri imx6 SoC via usb. I'm assuming that the imx6 is using 3v3 logic because it doesn't indicate otherwise, and ...
