All Questions
Tagged with nmos logic-gates
10
questions
-1
votes
2
answers
599
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How do you go from gate level to transistor level?
Is there a good method to go from circuit at gate level or truth table to transistor level, other than trial and error?
I have an example here to illustate what I am asking.
We have the function \$X=(...
0
votes
4
answers
891
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Details regarding PMOS and NMOS transistors used as gates
My lab instructor explained very briefly what transistors are and started by naming them NPN and PNP then switched to PMOS and NMOS and I (as well as my classmates) am very confused, I need someone to ...
- 181
1
vote
1
answer
1k
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Why not switching extra inverters with opposite MOSFETs in CMOS XOR gate?
Below you can see a CMOS XOR gate. I wonder why we do not change extra inverters like A' or B' with opposite MOSFETs.
For example, could not we just put the green construction in the place of red ...
user183701
-2
votes
5
answers
944
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Using Transistors as Logic Gates
I am curious if this could work. I have 3 inputs (A,B,C) and I know that Input A takes the longest to calculate. Is it possible to use single Transistors in place of normal AND Gates so that a signal ...
- 29
0
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2
answers
2k
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How to size CMOS transistors
I am new to CMOS technology and I am trying to learn about CMOS logic gates. I have a problem with transistors sizing. As far as I could understand the main idea is to obtain equal rise and fall times....
- 135
0
votes
1
answer
2k
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NMOS/PMOS logic vs. CMOS logic
With PMOS and NMOS, one can deduce that it is off, if
Vgs < Vt (NMOS) || Vsg < Vt (PMOS)
id = 0.
Now my question rests on the dependency of these conditions.
I know proving condition 1 ...
user91567
1
vote
2
answers
4k
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PMOS and NMOS in cut-off
I am confused regarding the voltages of NMOS and PMOS. For a NMOS, let us say it is in cut-off, thus making Id = 0. Then does that mean Vds = 0? I was initially under the assumption that Vds can be ...
user91567
0
votes
1
answer
467
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Tristate logic equivalent in NMOS logic
Suppose I have 3 signals generated by NMOS logic. Each of those signals has an associated enable pin that when driven high will result in the value of the signal appearing on the output (I should note ...
- 209
2
votes
1
answer
62
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Help with NMOS Gate question
In this picture, when v1 and v2 are 0, M1,M2 are on and M3,M4 are off. V_T(threshold) = 1.7V, V_DD = 5V.
Why is it that M1 and M2 are ON under these conditions? I thought when there is no power ...
- 31
2
votes
2
answers
20k
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Create a CMOS circuit from a logic function [duplicate]
I have to create a CMOS circuit from the logic function: F= ~A + B (notA or B). I made the truth table but I'm stuck here trying to make the CMOS circuit. Any ideas anyone? Thanks!
I know it's the ...
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