All Questions
144
questions
0
votes
1
answer
57
views
Non buffered CMOS logic gates working under load when using real components (LTSpice Sim)?
I'm experimenting with CMOS logic gates and have encountered something I am having a hard time understanding.
When I make an inverter using ideal components and measure the output, it works exactly as ...
- 165
1
vote
1
answer
113
views
How can I simulate driving a high capacitance MOSFET with a gate driver IC?
I'm trying to drive a MOSFET with approximately 2nF of capacitance, using a 1EDN7511B gate driver.
Following the data sheet sample circuit, I created this:
and tried to simulate it on LTSpice using ...
- 1,215
0
votes
2
answers
115
views
Dot parameters LTspice - Transconductance of MOSFET
Below is a very simple circuit to extract the transconductance value of the MOSFET.
As it is known, transconductance is known as Delta (Id) / Delta (Vgate).
For the gate voltage, I defined it as .step ...
- 405
3
votes
3
answers
1k
views
Strange pulldown resistor behavior with power MOSFET and Full Wave Rectifier in LTSpice
I've been having some trouble getting a pulldown resistor to behave as expected in LTspice. Here are two screenshots of my circuit.
This circuit has a full wave bridge rectifier convert AC (USA ...
- 33
1
vote
1
answer
38
views
Voltage input low of nmos inverter with enhancement load
I have the following schematic in LTSPICE
For each of these circuits I have to find the values for the VOH, VOL, VIL and VIH. To find the input voltages I observe the derivative of the V_out_NMOS ...
- 63
1
vote
3
answers
220
views
Unexpected output distortion when driving MOSFETs with SPWM in LTspice
The first picture below is the circuit diagram. SPWM was used, a full bridge structure and bootstrap circuit was used for the high side MOSFETs.
Datasheet IXTH88N30P
The carrier signal is 10 kHz and ...
- 405
4
votes
2
answers
2k
views
Why do I get 9V while the figure in the datasheet says I should get ~4V?
How do I get ~4V from Figure 9.1 below, when I simulate it I get around 9V. Am I doing something wrong?
The source of the original schematic "Figure 9-1" below is the Texas Instruments ...
- 2,391
1
vote
0
answers
69
views
How do I use ideal MOSFET model in LTspice? or How do I set voltage in node without voltage source?
I want to simulate the principle of 1T1C DRAM cell. But if I model voltage source in Bit line, bit-line voltage is set by its input signal. So I want to seperate bit line, using ideal MOSFET component,...
- 11
1
vote
1
answer
54
views
How to interpret Ids of low-side FET in phase leg configuration?
I am simulating a phase leg configuration as shown below using a [GS66508T][1] GaN FET. Does anyone know if the circuit is working correctly according to the current plot?
There is current spike above ...
user369787
3
votes
1
answer
84
views
Quadruple MOSFET charge pump simulation does not work as expected
Background
Source claims that this MOSFET-based charge pump circuit should work. The schematic looks logical and I was able to reason my way through its expected behaviour. I tried simulating the ...
- 904
1
vote
2
answers
85
views
Modelling a Floating Gate Transistor
Does anyone know of a simple circuit diagram to implement in the likes of LTspice to show the operation of a floating gate transistor?
Would a capacitor on the gate of a standard transistor do the ...
- 91
0
votes
2
answers
65
views
Help troubleshooting Mosfets in Switching Circuit
I've been trying to design a simple circuit to switch between two Supply rails (3.3V_SW & Vbat) while giving one of them a higher priority (3.3V_SW). The circuit in simulation is showing to be not ...
- 79
0
votes
1
answer
65
views
Simulation time for Full bridge
This is a full bridge circuit which I am trying to simulate in Ltspice with a snubber. When I use ideal switches instead of MOSFETS, the simulation works fine. But when I use the real mosfet models, ...
- 275
0
votes
0
answers
103
views
CML Latch simulation in LTSpice
I am trying to simulate a CML Latch in LTSpice (schematic below), but the simulation results do not seem right. I am using N_50n transistors from BSIM4 model. L = 60n for all transistors, W = 10u for ...
- 1
1
vote
0
answers
90
views
MOSFET parasitic turn-on
I'm simulating a circuit which uses a high-voltage SiC N-channel FET to discharge a large voltage (something close to the breakdown voltage of the FET, 1.7 kV). The power supply for the circuit is a 1 ...
- 21