All Questions
Tagged with logic-level logic-gates
18
questions
-1
votes
2
answers
92
views
Wired AND and OR question, logic levels?
In the "wired AND and OR" gates pictured can anyone explain what the voltage levels will be for each function?
For AND, I see the output is A*B and for OR, A+B. Is this correct? Also, is ...
- 115
0
votes
1
answer
46
views
Ensure that cable is not disconnected from my custom board
I designed a custom board, the board includes stm32 that turns on a control voltage that operates SSR and the SSR goes to the load:
CTR comes from the GPIO of STM32.
in my custom board, there is some ...
- 441
2
votes
0
answers
87
views
How to understand this combinational cyclic circuit made of interconnected SR latches?
I'm trying to understand the following circuit, or better said, what must be the approach to analyze other similar ones:
What I'm doing for now is forget about the clock signal and the ...
- 1,259
1
vote
1
answer
323
views
Why does the 74LS32N behave like an AND gate?
First of all I am a beginner.
I am practicing with the 74LS32N (OR Gate) IC , I noticed that it behaves like an AND gate instead of an OR Gate.
Only when both the inputs are 1 , the output is 1 , (Led ...
- 11
0
votes
1
answer
186
views
74HC08N doesn't latch [closed]
I am using the 74HC08N chip. Why doesn't the first AND gate latch itself?
I have connected the output of the first AND gate to its own input.
I have used two resistors, the one on top is a pull-up and ...
- 11
1
vote
1
answer
310
views
In a NOR gate not connected to any power supply, how can the output be '1' if both of the inputs are '0'? [duplicate]
I was reading about SR Latches and this very weird (and silly) question popped up in my head.
Here, when A and B is 0, then Q is 1.
Suppose that this NOR gate is lying in air, not connected to any ...
- 113
2
votes
2
answers
366
views
Multi-level circuit simple NAND conversion: Why keep non-NAND symbols?
I am working on understanding the NAND conversion. I have just got the basics of two-level NAND conversion, and when I went to the book example for a multi-level NAND conversion it used solved an ...
- 29
0
votes
1
answer
107
views
Compatibility of devices with different voltage thresholds/noise margins/static disciplines
tl;dr included at the bottom.
Suppose we have two logical buffers from different logic families, where buffer A drives buffer B. Buffer A has the following voltage thresholds: \$V_{OH}=8\ V\$, \$V_{...
- 675
0
votes
2
answers
199
views
SR Latch internal conflicts
it is known that "11" are invalid inputs for a SR Latch. But I do not understand the reason of that. I cannot see the electrical conflict in this structure:
If R = 1, its NOR gate will give 0, for ...
- 3,550
1
vote
1
answer
988
views
Can a 74AHCT IC be a drop-in replacement for 74HCT IC
I have a circuit in which I interface a radio module running on 3.3V indirectly from a 5V supply.
I use a regulator to provide the 3.3V module VCC and the data is exchanged between both circuits ...
0
votes
1
answer
131
views
In logic levels, why are the driver and receiver depicted as inverters?
In Digital Design and Computer Architecture (Harris and Harris), the following schematic is given , in discussing logic levels.
Why are the driver and receiver depicted as inverters?
- 131
0
votes
2
answers
124
views
Are D flipflop inputs and clock thresholds the same for a given logic family?
I'm using an SOIC20 74ACT574 octal flipflop in a design.
Vcc is 5 V, and GND is 0 V. The datasheets give V_IH (logic high input, guaranteed minimum) as 2.0 V and V_IL (logic low input, guaranteed ...
- 1,104
1
vote
4
answers
5k
views
Can you damage logic gates by connecting two outputs together and powering one?
As the title says, would this cause problems in a circuit, and if so, how do you get around it (other than connecting them both through an OR gate)?
Furthermore, could you stop this with a buffer? ...
- 11
0
votes
1
answer
432
views
How can I have an ECL logic input for a CMOS logic gate
I'm working on a triggering system that uses a comparator to check if the signal is below a threshold value. I found a great comparator for the job, except its output is ECL logic. I wanted to use the ...
- 23
1
vote
1
answer
2k
views
Unstable output in VT pin of HT12D decoder
Hi everyone,
I have been recently working on a RF operated water pump project. For this purpose i bought a RF RX and TX module which has HT12E and HT12D chips as encoder and decoder.
The D8 (Dout) ...
- 399