Questions tagged [deserialiser]
The deserialiser tag has no usage guidance.
16
questions
0
votes
1
answer
37
views
LVDS Display connected to Deserializer clarification needed
I need to use an LVDS display in my project.The pin configuration of LVDS display is given below(I can't share P/N here due to NDA).
As per my knowledge the PIN No 18 and 19 are Horizontal sync and ...
- 2,593
0
votes
1
answer
24
views
Is it possible to send CAN BUS information using FPD link?
I am using below serializer and de serializer in my design. The communication is happening via FPD LINK.
The block diagram is given below.
I have a CAN bus connected between the these two boards.
My ...
- 2,593
1
vote
1
answer
141
views
Common mode choke placement for good EMC performance
I am interfacing a deserializer with Quectels smart module.
The CSI lines of the deserializer are connected to the CSI lines of smart module.
A common mode choke is placed in between them. The ...
- 2,593
0
votes
2
answers
162
views
Why is the Gb/s usually matched with the GHz for SDI?
My knowledge in electronics and RF(because high speed data) is very surface level but attempting my best.
I'm attempting to do an application which utilizes 3G SDI, but am not understanding why there ...
- 1
1
vote
2
answers
41
views
Voltage on the Serial Link and Parallel Resistor Value
This question is related to the previous question that I had over here
I found the serializer that I am using. It is over here
From the above serializer datasheet, on page 9, I found that the maximum ...
user220456
2
votes
1
answer
86
views
Voltage on the serial link
I am using this MAX9278 deserializer.
The inputs to the IN+, IN- pins of the deserializer are twisted pair inputs.
On the IN+ and IN- serial link, I have 2 AC coupling capacitors of 220nF 50V on each ...
user220456
0
votes
1
answer
46
views
GMSL Deserializer to LCD Link Rate
I need to calculate the Link Rate for my GMSL Deserializer which is connected to a 800 * 480 TFT Display.
In that case, I stumbled upon this Article
On the last few lines, they are asking to multiply ...
user220456
0
votes
0
answers
50
views
Deserializer Datarate calculation
I am having this MAX9278 deserializer IC.
The input to the pins +IN and -IN is a twisted pair input and therefore, it is a differential signal. I have configured the CX/TP pin to low since it is a ...
user220456
0
votes
0
answers
83
views
Coax or STP input to the Deserializer
I have this MAX9278 deserializer.
I am planning to give Shielded Twisted Pair (STP) input to the IN+ and IN- pins of the deserializer instead of COAX input.
Can someone help me to let me know what ...
user220456
0
votes
1
answer
54
views
Setting the address of Deserializer
I have this MAX9278 GMSL1 Deserializer.
I have 3 below questions:
How to configure the CX/TP pin if I want to use the coax mode?
And how to arrive at the address of the deserializer if I connect ...
user220456
0
votes
0
answers
39
views
SPI Configuration in TFT
I have a TFT which requires SPI Communication interface to get it configured.
My questions :
When we say, "configure the tft", what do we actually do? Do we set some bits or erase some bits ...
user220456
0
votes
1
answer
151
views
What is the meaning of Change in Output Offset Voltage between complementary output states
I have MAX9278 deserializer IC which is connected to a 3.1inch TFT display 800 (W) * 480 (H).
Deserializer provides 4 LVDS lanes and 1 clock to the display.
While I checking the electrical voltage ...
user220456
0
votes
1
answer
42
views
What are the main parameters to check display with display controller
I have MAX9278 deserializer IC which is connected to a 3.1inch TFT display 800 (W) * 480 (H).
Deserializer provides 4 LVDS lanes and 1 clock to the display.
What are the major parameters that I need ...
user220456
0
votes
0
answers
70
views
How to provide 3 options (pull-up, pull down and Open) in an IC
I have MAX9278 Deserializer IC.
I have 2 doubts.
Doubts :
I am performing the schematic now. Below, I need to provide options for both 24-bit, 27-bit and 32-bit.
How to provide the provision for all ...
user220456
2
votes
1
answer
584
views
SDLC Frame Check Sequence details
In the Synchronous Data Link Control (SDLC) protocol, the frame contains a "frame-check-sequence" (a CRC). The protocol contains a number of other implementation details, such as NRZI encoding, and ...
- 1,101