I'm laying out a stacked PCB where I have 3 or 4 boards stacked on top of each other with signals propogating down with female/male headers (think Arduino shields). Shared control signals are propagating down from the top (logic) board to the lower daughter boards, with certain runs being 12 inches or more between the logic out and logic in.
Is it necessary to buffer TTL signals, and is there a maximum trace/path length before when its important?
Oh boy, where to begin...
Basically, there is this whole field called "signal integrity" that directly relates to what you are asking about. SI is a complex topic that takes years to really comprehend and wrap your head around. There is a lot of information on the net about SI, and honestly most of it is wrong, misleading, or misguided. Unfortunately, knowing this stuff is essential to getting digital systems to be robust and reliable. Every EE should know this stuff.
The best guide for this is the book High Speed Digital Design: A Handbook of Black Magic. A highly recommended book, and worth every penny!
There is no way that I can give you a good overview of the things you need to know about SI. The topic is that big and complex. But let me give you some random bullet items that hopefully will, with a good book, point you in the right direction.
I also want to stress again that most things you find on the net get some or all of this wrong. Arduino stuff especially. Get a good book, and use that as a solid foundation. Oh, most books have major errors too. The book I mention is very good and is considered by almost everyone to be the golden standard.
Is it necessary to buffer TTL signals, and is there a maximum trace/path length before when its important?
Are those actually TTL signals? In most cases, the only way to get TTL signals is to obtain them from the outputs of 74xx, 74Hxx, 74Lxx, 74Sxx, 74ASxx, 74Fxx, 74LSxx and 74ALSxx logic families, bipolar PAL and GAL chips, bipolar PROMs and gate arrays, and not very much else.
Many people use the term "TTL signals" to mean 5V CMOS logic levels.
Modern digital electronics are usually all CMOS, and while the signals remain TTL compatible, you have neither TTL outputs nor TTL inputs, so things are a bit different.
The maximum bus/signal length is determined by the frequency content of the signal, and that is determined by the load capacitance, parasitic capacitance on the signal line, source (output) impedance and rise/fall time. It is, in most circumstances, the short rise/fall times that cause the most problems on otherwise "low" frequency signals. If you got a 1kHz square wave coming out of fast CMOS outputs, it may have 100V/us slew rates, and those by themselves require all the necessary care to retain their integrity.
Typically, you'll want to slow down the edge rates to just what the receiver requires. E.g. if you're driving an LED, then put the series resistor right at the output, and perhaps a small bypass capacitor - say 100pF to ground - to slow the edges down. The shield boards will require "decent" edges for, say SPI signals and other clocked data, but e.g. I2C is rather benign and not very sensitive to trace length itself. Asynchronous signals typically only need to obey maximum rise/fall time limit placed by the receiving IC, say 1us for 4000-series CMOS logic.
In short: in almost all cases, with modern fast-switching digital outputs, you'll want to limit the slew rates to just slightly above the maximums required on any "long" signal run, and even on short signal runs that interface to analog circuitry e.g. ADCs and DACs.
For actual TTL signals coming from bipolar TTL outputs and driving TTL bipolar inputs, you'll want to consult TI's TTL Data Book for Design Engineers, and Don Lancaster's TTL Cookbook. There's quite a bit of attention to detail necessary to make TTL work the best it can, in terms of signal integrity, especially with so many sub-families, a variety of bus loads, etc.
You've got a couple of things to worry about. One is the voltage drop across longer and longer lengths of wire. Too much drop and you may be below the threshold of the receiving circuit to recognize a logic state.
The other thing is the variability of the level on the line. If you are sending a constant signal, ok, if you are sending a signal that goes up down up down, say once a second (slow enough so you could see with your eye if you hooked up a light to it)' ok, but really anything above that and you have to consider the frequency response of your line, it's ability to react to fast changes and get the same signal on the receiving pin. This depends on capacitance, inductance, etc...
This situation is exactly why they make RS232, etc.
