Why don't we use an integrator as the loop filter of a PLL?

Question

In a book on phaselock that I was reading, it mentioned that ideally, one would use an ideal integrator as the loop filter of a PLL. Since we can implement integrators with op-amps, why don't we use that as the loop filter? The schematic the book provided looked something like this (I got the image from google), and to my knowledge, you wouldn't normally have R2 if it was purely an integrator. Why don't we use op-amp integrators as the loop filter in PLLs, and what is R2 doing in this loop filter?

Answer 1

The VCO frequency to phase function is an integrator. An integrator has exactly 90 degrees phase shift. If we simply added another plain integrator, then we would have 180 degrees phase shift. That means guaranteed instability. That's why if we do include something 'integrator-like' in our filter, it's a broken integrator, broken back to lower phase shift above some frequency.

Now paradoxically, the component R2 that you want to eliminate is arguably the most significant component in the filter. Together the with VCO gain and the PSD gain, it defines the loop bandwidth.

We can take the three capacitors and vary their values. As long as we vary their values in the stable direction (C1 and C3 lower, C2 higher), the loop bandwidth will not change substantially. We use C2 to improve PLL behaviour like improved tracking at low modulation frequencies, and C1/3 to improve reference rejection at high modulation frequencies. However the fundamental loop parameter loop bandwidth is set by the total gain round the loop. R2 sets the loop gain by setting the PSD's current output to VCO's tune voltage ratio.

Given that the VCO's frequency to phase integrator gives us a minimum of 90 degrees shift in the loop, the rest of the loop design for stability is easy. However many capacitors we have in the loop filter, together they must contribute significantly less than 90 degrees total phase shift into the loop. As there are three, let's budget 15 degrees each, leaving us 45 degrees phase margin (neglecting PSD latency which is usually OK). Given that we have chosen a loop bandwidth to fit the loop's purpose, and chosen a value of R2 to get that loop bandwidth, we now choose C2 to give us 15 degree phase shift at that loop bandwidth frequency. Choose R3/C3 to give another 15 degrees at the same frequency. Choose R1/C1 for another 15 degrees.

We now have a stable PLL design, without going anywhere near damping ratios and those horrible equations you find in PLL design papers. The capacitors will alter the loop bandwidth very slightly. A bit of tuning might be needed to get the highest speed settling. But, with little maths, we have a stable loop of substantially the right bandwidth. AND, we understand how we got here, so we can make changes not covered in those horrible equations.

If for instance the VCO has a very non-linear tuning curve, we know how to accommodate the change of loop bandwidth without losing stability. Take the worst cases, and move the break points of the filter capacitors in the stable direction until they never contribute more than 15 degrees.

If the reference has a very large degree of noise on it which we need to reject, and C1 and C3 don't cut it, we might want to change C3 into a 3rd order CLC passive filter in the VCO tune line. No problem, we now have 5 filter elements, so make them 9 degrees each for the same 45 degrees filter phase shift.

Answer 2

When the PLL has locked the whole system can be regarded as a linearized system. Hence, all rules derived from system theory for feedback loops can be applied. At first, we realize that the "plant" to be controlled can be described by the phase transfer function in the s-domain:

Hp(s)=PHI(s)/Vc(s)=Ko(1/s)

(Vc: control voltage; PHI: output phase; Ko: VCO constant).

When the closed loop would contain another integrator as the loop filter this would introduce another 90 deg phase shift (in addition to the 90 deg caused by the plant). This 180deg phase shift would violate the stability condition (or at least reduce the phase margin to an unacceptable small value).

Therefore, the loop filter must contain a zero and - in most cases - is realized as a PI-controller (as shown in the diagram).

When properly designed, the loop gains phase function will provide enough margin (distance to 180deg) at the critical frequency where the loop gain magnitude crosses the 0dB- line.