We're building a device which takes its input power from a 12VDC wall wart PSU, and has a metal chassis. We just passed preliminary EMC/EMI test, but in the ESD test an 8kV jolt to the chassis killed the whole device. How do I fix this?
The electronics consists of two PCB's:
- a mainboard which uses two SMPS's to generate the supply voltages, contains a microcontroller, quite a lot of analog circuitry and backpanel connectors (DC input jack, two MIDI connectors, seven quarter inch audio jacks, and an entirely isolated USB connector with it's own ground, connected to the rest of the circuitry via a capacitive isolator IC)
- a UI-board, which connects to the mainboard via a FFC cable carrying the voltages from both of the SMPS's, ground, and a bidirectional UART signal. The UI board has buttons, LEDs, potentiometers, a display and another microcontroller.
The metal chassis is two-part, a top chassis which is the front panel, back panel and rear panel, single piece aluminum, and a bottom chassis which is a flat steel plate. The two parts do not directly connect electrically as measured by a multimeter (though they are very close, so I'm not sure that a high-voltage ESD event couldn't skip between them). The sides are plastic.
Both of the PCB's have a single uninterrupted ground plane. The chassis connects to the signal ground at three locations:
- a grounding bracket at the rear panel of the unit, connected directly to the mainboard PCB ground and with a screw to the top chassis. This is located right next to the +12V DC input.
- Two mounting points at the bottom of the device, connected directly to the mainboard PCB ground and with a screw to the bottom chassis. These are located relatively at the middle of the PCB, one of them approximately at a straight line from the DC connector to the SMPS's, the microcontroller and finally on to the grounding point (in case that might matter).
The UI-board has a silicone key mat on top of the buttons and LEDs, plastic caps on top of the potentiometers, and the display is covered by a plastic plate. The potentiometers are not directly electrically connected to the chassis, as measured by a multimeter.
During the ESD test, the test engineer was zapping away at an 8kV setting on the ESD gun at the silicone keypads. He repeatedly hit the metal front chassis by accident since the silicone pads are quite small, which the device withstood several times. However, suddenly the whole thing went dark after one of these zaps.
What happened? How can I fix this?
Further details:
Note that according to the standard, metal parts should be zapped only by 4kV, whereas plastic parts with 8kV, but the test engineer was complaining that it's difficult to not have the voltage jump to the panel, as was happening.
After some investigation, it turns out that the 12V wall wart was dead, i.e. no voltage output when measured with a voltmeter. Replacing that with a lab supply had the the device shorting out such that a 1A current limit the voltage would rise variously to 1.46V or 0.82V. The behaviour was the same when removing the mainboard from its case to eliminate the effect of any damage to the UI-board. Curiously, the mainboard was temporarily revived when I was touching it to see if any components got hot, showing normal current consumption at 12V (0.45A). However, after a while it stopped working again and could not be revived the same way.
Details on connectors
- The connectors are isolated from the chassis: the USB-connector has a metal shell, which is separated by a small gap from the chassis, other connectors have plastic enclosures (part numbers and datasheet links UJ2-BH-W1-TH, KCDX-5S-N2, KLDX-0202-AP-LT, NRJ6HF-1)
Partial schematics
PSU input section:
Wall wart info plate:
The wall wart is a generic China sourced +12V center-positive wall wart, datasheet
From the datasheet, note that the wall wart is specified for 4kV direct discharge, and 8kV air discharge. At least the fatal zap was probably an air discharge, but it is quite possible that some of the accidental zaps might have been touches.
Device assembly
PCB sections, UI-board is located on top of Mainboard:
PCB stackup, mainboard:
- Top: high speed signals, other signals, components
- Inner 1: GND, only split is separate GND under (capacitively isolated) USB
- Inner 2: power, planes split heavily into several different supply voltages, and some power as traces
- Bottom: signals
PCB stackup, UI-board:
- Top: high speed signals, other signals, components
- Inner 1: GND, no splits
- Inner 2: almost intact +3.3V digital power, one wide trace +3.3V analog power around the edges
- Bottom: (very few) signals
Chassis assembly, simplified:
Added later
Hypothesis
I just spoke with the test engineer: in the ESD-test setup, the current is discharged through a plastic sheet under the device, to a large metal ground plane on the test table. As it happens, currently the most direct path is along the front chassis, through the grounding screw, along the ground plane on the mainboard under the SMPS and MCU, to the grounding point that connects to the bottom chassis. This does appear to rhyme with the symptoms, i.e. mainboard SMPS appears damaged (takes way too much current, even though I can't find a direct short with a multimeter when not powered on), and intermittently mystically revives only to fail again.
Potential fix:
Connect the top and bottom chassis directly without the mainboard PCB in between, to give the current another path to the bottom. Possibly even not connect the grounding points at the bottom to the PCB ground?
Feedback on the hypothesis and potential fix are welcome
Further developments:
Using a borrowed ESD gun and a makeshift test station, we ran some of our own tests, according to IEC 61000-4-2 (obviously, to our best one-day-effort, so these are not accredited laboratory results).
Importantly, whereas in the original test the engineer used a carbon fiber brush to remove accumulated charge, we used a grounding cable with bleeder resistors (as preferred by the standard), since we weren't convinced that the brush removes charge through the paint on top of the case.
- The wall wart survived the test as specified in the standard, i.e. 10 times 4kV contact to the negative conductor, 10x 8kV air discharge to the plastic, occasionally jumping to the negative conductor.
- A device with the fix applied via a jumper cable from top chassis to bottom chassis, and disconnecting the internal connection through the signal plane survived the test (10x 4kV contact, 8kV air discharge to all non-conducting parts (which did clearly jump to the case several times)), survived the test.
- an unmodified device also survived the test.
So right now the possibility of over-testing, i.e. inadequate charge removal, is looking likely. We'll go back to the actual lab on friday, so then we'll know more.
