Why should the Vce be half the value of the supply source?

Question

For a BJT amplifier biased to operate in the active region; I think that the statement "the voltage Vce is half the value of the supply source" is incorrect. Because I know that such a thing is not usually valid in amplifier circuits. Am I wrong?

Answer 1

I don't know what you mean by:

I know that such a thing is not usually valid in amplifier circuits

You don't explain how you know this, or provide an example, so I can't comment on that. But you are wrong, and I can show you examples of why.

A "signal" in this context means a potential that is able to fluctuate, upwards and downwards in value, but any circuit producing such a signal is constrained by its own power supply potentials. Circuits generally can't produce a potential that lies outside its supply potentials (with certain exceptions like DC-DC converters and charge pumps).

Knowing these output constraints, it often makes sense "center" the output (set the DC operating point, or quiescent voltage) half-way between the possible extremes, so that it may fluctuate equal amounts above and below that mid-point.

When doing this, quiescent \$V_{CE}\$ ends up near half of the supply potential difference, regardless of collector and emitter resistances. Modelling the transistor as a switch (left and middle), or as some arbitrary impedance \$R_{CE}\$ (right); the three transistor states are:

^{simulate this circuit – Schematic created using CircuitLab}

Power supply potentials are \$V_P\$ (positive) at P and \$V_N\$ (negative) at N. I'll ignore base current, assuming collector and emitter current to be equal, \$I_C = I_E = I\$.

It may be obvious that \$V_{CE}\$ (the difference \$V_C-V_E\$) can vary between zero and the full supply potential difference \$V_P-V_N\$. Intuitively, with Q1 off, no current flows, leaving zero potential difference across either resistor, and \$V_{CE}=V_P-V_N\$. With Q1 fully on, there's near-zero potential difference across it, and \$V_{CE}=0\$.

To treat this more formally, start with KVL and Ohm's law to describe this system:

$$ \begin{aligned} V_P - V_N &= V_{RC} + V_{CE} + V_{RE} \\ \\ V_{CE} &= (V_P - V_N) - V_{RC} - V_{RE} \\ \\ &= (V_P - V_N) - IR_C - IR_E \\ \\ &= (V_P - V_N) - I(R_C + R_E) \end{aligned} $$

With Q1 in saturation, output potential is at a minimum, and collector/emitter current \$I\$ is at a maximum:

$$ I_{SAT} = \frac{V_P-V_N}{R_C + R_E} $$

When Q1 cuts off, output potential is at a maximum, and current \$I\$ falls to:

$$ I_{CUT} = 0 $$

Corresponding \$V_{CE}\$ for these two states are:

$$ \begin{aligned} V_{CE(SAT)} &= (V_P - V_N) - I_{SAT}(R_C + R_E) \\ \\ &= (V_P - V_N) - \frac{V_P-V_N}{R_C + R_E}(R_C + R_E) \\ \\ &= (V_P - V_N) - (V_P - V_N) \\ \\ &= 0 \\ \\ \\ \\ V_{CE(CUT)} &= (V_P - V_N) - I_{CUT}(R_C + R_E) \\ \\ &= (V_P - V_N) - 0 \times (R_C + R_E) \\ \\ &= (V_P - V_N)\\ \\ \end{aligned} $$

So \$V_{CE}\$ varies between the full supply potential difference \$V_P-V_N\$ and zero. The goal is to have a quiescent \$V_{CE(Q)}\$ half way between those two:

$$ V_{CE(Q)} = \frac{V_P - V_N}{2} $$

A couple of examples to illustrate. The output of the common-emitter design below cannot be above +12V, or below -4V, since those are the limits imposed by the power supply:

^{simulate this circuit}

In this case the supplies are 12V above ground and 4V below it, or \$V_P=+12V\$ and \$V_N=-4V\$, so these are the expected minimum and maximum to be seen at the output:

With \$V_{IN}\$ being a 100mV sinusoid, this is clearly driving transistor Q1 out of its active region, into saturation or cut-off, the result being that \$V_{OUT}\$ is "clipped" between extremes of +12V and -4V.

Knowing these output constraints, we will "center" the output (set the DC operating point, or quiescent voltage) half-way between those extremes, so that it may fluctuate equal amounts above and below that mid-point.

I've chosen R2 and R3 here to set that center potential mid-way between +12V and -4V:

$$ V_{OUT(DC)} = \frac{V_N + V_P}{2} = \frac{(-4V) + (+12V)}{2} = \frac{+8V}{2} = +4V $$

This is shown on voltmeter VM2, and is a value with respect to ground. The quiescent potential difference \$V_{CE}\$ is:

$$ V_{CE} = V_C - V_E = V_{OUT(DC)} - V_N = (+4V) - (-4V) = 8V $$

Quiescent \$V_{CE}\$ is shown on voltmeter VM1, and is half of the total supply potential difference of 16V.

This is a terrible circuit, by the way, highly dependent on transistor characteristics, and almost certainly won't show these values if you built it. It's only good to illustrate.

It may be that you don't need quiescent output to be half way, because the output is expected to have a very small amplitude, in which case you do not care so much about the output getting close to either extreme. That's an exception to the "\$V_{CE}\$ is half of the supply" condition.

More often we employ an emitter degeneration resistor, to linearise response and set voltage gain precisely. Here we have gain \$\frac{R_C}{R_E}=2\$:

^{simulate this circuit}

I've reverted to a single-ended supply with potentials 0V and +12V. The lower output constraint is no longer the negative supply (0V in this case), due to the presence of \$R_E\$.

As an estimate, the extreme conditions are when the transistor is saturated, \$V_{CE}\approx 0\$, acting like a closed switch with no resistance, and cut-off, when that switch is open. Those two states can be modelled as follows:

^{simulate this circuit}

Now we have output bounds of \$+4V < V_C < +12V\$, and if we wish for the output to be able to swing upwards as much as it can downwards, then we need the DC operating point to be at the mid-point:

$$ V_{OUT(DC)} = \frac{V_{OUT(MIN)} + V_{OUT(MAX)}}{2} = \frac{(+4V) + (+12V)}{2} = \frac{+16V}{2} = +8V $$

Again, quiescent \$V_{CE}\approx 6V\$ (see VM1) is half of the total supply potential difference of 12V, even though we have centered collector potential well above +6V.

We can verify that our calculations are correct with another simulation. This is the output \$V_{OUT}\$ with the input slightly over-driven to cause output clipping at those extremes:

Answer 2

The quiescent (or average) value of \$V_{CE}\$ is usually chosen to be half the rail voltage. This allows AC voltages to sit at the mid-rail and be permitted to rise without asymmetrical clipping.

Answer 3

This statement (Vce = Vc = Vcc/2) is valid for a CE stage with grounded emitter. If there is an emitter resistor inserted, then Vc = (Vcc - Ve)/2 + Ve = (Vcc + Ve)/2.

Answer 4

It depends essentially on a few considerations:

• What's the available power supply voltage difference across the circuit?
• What's the input signal voltage range?
• What's the gain required? (Or, what's the output signal voltage range?)
• What level of signal distortion is permitted?
• What's the circuit's operating temperature range?
• What's the design range for transistor parameters used in the circuit?

Obviously, if the output is DC coupled to the next stage then the rule is tossed out on its head because the next stage's requirements determine everything and the rule of thumb becomes mostly useless. Let's discount that and assume the output is AC coupled.

Things are less critical when the available power supply voltage difference across the circuit is very large. In such cases, the simple rule can be applied without thinking much. This is because there's lots of working headroom for both the collector and emitter. The emitter headroom allows significant compensation for operating temperature variations, so that's no longer much of a problem. The collector headroom helps to minimize collector current variation and thereby reduces output distortion and assuming it is also large with respect to the output swing these two issues, distortion and room for the output, are no longer much of a concern.

So large power supply voltages sweep away a number of concerns and the rule can be readily applied without much concern. That doesn't mean it has to be used. But it can be without getting bogged down with other problems listed above. And it has the advantage of being easy to apply without risking the remaining considerations.

It's in the case where the available power supply voltage difference across the circuit is small that the rule should be thrown out -- or, at least, set aside while other concerns are examined more closely.