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Assume you have a four layer board.

  1. Signal
  2. GND
  • Dielectric
  1. VDD
  2. Signal

And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer.

Question

The reference plane for the 4:th layer is the 3:rd plane, which has a potential lager than GND volt. The VDD don't have to be 3V3 volt, it can be voltage for DDR memory as well.

But once you're routing your track from 4:th layer to 1:st, you're also changing the reference plane to GND, which is now 2:nd layer.

Should you place a copper plane at the 2:nd layer which has the same voltage potential as the 3:rd layer?

Update:

This is one example where I add a copper plane and asign VDD onto it. Now the stack is

Signal/GND GND GND Signal/GND

Perhaps this is not good at all? I need to get the capacitor-effect? The C144 is a 10 uF capacitor.

enter image description here

If I cover the second layer with the first layer like this.

enter image description here

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2 Answers 2

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Should you place a copper plane at the 2nd layer which has the same voltage potential as the 3rd layer?

The plane's DC level is irrelevant.

It's the plane's proximity and AC impedance to the associated tracks that is important. That plane's capacitive connection to the actual GND plane makes it a suitable substitute for GND.

However, if the power plane voltage is noisy with respect the GND then it could cause problems. Solution is good decoupling between GND and power plane at several points.

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  • \$\begingroup\$ So you're telling me that I should use the most noise free plane as the reference plane? \$\endgroup\$
    – euraad
    Commented Jun 5 at 15:27
  • \$\begingroup\$ No, I'm not saying that. GND by default has to be the most noise-free plane and that should always be regarded as the reference plane but, it's permissible to use power planes providing they are not noisy AND, they can be made less noisy (to an acceptable level) by adding decoupling capacitors at several points @euraad \$\endgroup\$
    – Andy aka
    Commented Jun 5 at 15:48
  • \$\begingroup\$ So adding copper and give it the same voltage potential, is not a common method to do, just because you want GND or VDD for a specific trace for all lines? \$\endgroup\$
    – euraad
    Commented Jun 5 at 16:29
  • \$\begingroup\$ I don't understand what you are asking me @euraad \$\endgroup\$
    – Andy aka
    Commented Jun 5 at 16:30
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    \$\begingroup\$ @Andyaka I understand the idea now. The potential voltage of the reference plane is not relevant and the reference plane should be noise free as much as possible and very close to the signal plane. Thank you. \$\endgroup\$
    – euraad
    Commented Jun 7 at 9:27
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No, the referece plane potential does not have to match.

The signal is AC so the DC does not matter, but the two reference planes must be well coupled together.

It means that if both reterence planes are GND, you can just use GND vias between planes right next to signal vias, so that the signal going vertically between top and bottom layer, there is a top to bottom return path between layers 2 and 3.

If you have a VCC and GND as reference planes, you can provide a good coupling between them with a capacitor right near the signal vias.

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  • \$\begingroup\$ So in this case, when I use plane 2 as VDD_DDR with a coupling capacitor and the plane 1 as GND, then it's fine? \$\endgroup\$
    – euraad
    Commented Jun 5 at 19:47

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