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I want to design a layout for MSP430FR6047 and I was reviewing a reference design form TI for MSP430FR6047 Evaluation board, then I noticed the are 4 different GNDs as follows: (USSXTAL_GND, TARGET_GND, XTAL_GND, USS_GND): enter image description here

And all the three GNDs (USSXTAL_GND, XTAL_GND, USS_GND) finally are connected to TARGET_GND as follows:

enter image description here

enter image description here

enter image description here

The gap on the connection seems to be very tiny, but in the fabricated board they are connected to each other:

enter image description here

Would you please let me know why? As far as I know it is not a good idea to have split grounds in a PCB based on recent literature for PCB design, so what was the reasoning behind this?

Reference: https://www.ti.com/product/MSP430FR6047?utm_source=google&utm_medium=cpc&utm_campaign=epd-null-null-gpn_en-cpc-pf-google-wwe&utm_content=msp430fr6047&ds_k=%257B_dssearchterm%257D&DCM=yes&gad_source=1&gclid=Cj0KCQjwpNuyBhCuARIsANJqL9OSCvFIJkRrUBK74MDoqPl5w4TU3AwboTkBaL8FYsoP0Ul27DyXcfEaAt7SEALw_wcB&gclsrc=aw.ds#tech-docs

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2 Answers 2

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I imported the PCB files into KiCad and as expected, the PCB editor shows it as a solid copper plane.

In the schematics a net tie is used, so the different ground planes are really connected even if they have different names.

The gap may just be a drawing glitch, or intetional visual element like a line with no width on some non-copper/documentation layer.

The grounds are not split as in disconnected from each other. There are just multiple ground plane areas that are connected together where it best suits the design.

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  • \$\begingroup\$ @ Justme thank you very much for investigating the PCB files, Yes, you are right, I agree, would you please let me know what would be the benefits of using different islands as GND and different Nets of GND and the finally connect them together? I would Just use one net name as GND and pour a uniform GND polygon, I'm still trying to understand why? even if these islands as you mentioned are connected together at the end. \$\endgroup\$
    – Andromeda
    Commented May 29 at 13:19
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    \$\begingroup\$ @Andromeda There's two things at play here. Basic rules of designing grounds planes are same for wires, don't allow noisy digital currents run on same wires as sensitive analog currents, or you measure the added noise. So the first point is to partition the grounds so that noisy return currents do not run through areas that have sensitive analog circuitry. The second point is to choose the method you implement it, like do you add virtual components to schematic and have different names for different ground pours, or do you start drawing the shape of ground plane using polygons. \$\endgroup\$
    – Justme
    Commented May 29 at 13:35
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They are "net ties" which are used to tie together different parts of the same electrical net in a way that controls how current flows. It is a way of capturing design intent so it does not get lost between schematic capture and layout.

enter image description here

In this case, the grounds have separate net names and are tied together using this "component" which does not show up on the BOM and is basically a copper strip connecting two different nets. That draws the attention of the layout person to where the current flow takes place. The component designators (eg. NT1) are also supressed. Here's what it looks like on the board without the poly pours and with the designator enabled:

enter image description here

This is quite a common technique in precision analog and mixed-signal designs.

The net tie itself is just two pads 30 x 50 mils exactly 30 mils apart, so they are touching. It is also marked as a net tie to keep the DRC from complaining about shorted nets.

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    \$\begingroup\$ I should add that while it does capture the intent, such as having a separate ground plane for the crystal, it fails to provide details how to implement it. For example, the crystal ground plane is implemented exactly opposite to how it is usually done. Here, the global supply ground plane and MCU oscillator ground pin meet at the crystal, so MCU pin currents flow through crystal ground plane. Usually, the crystal ground plane and global ground plane would meet right at the MCU pin, so MCU pin currents do not flow through crystal ground plane. Either this is an error or a delibrate decision. \$\endgroup\$
    – Justme
    Commented May 30 at 5:09

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