This sounds like a prime application to apply DFT (Design For Test) principles.
The more basic elements of DFT are such steps as, adding testpoints for all nets, or at least those that need them; making sure they're accessible (size, spacing, one sided if possible, etc.), and so on; which I'm guessing are already in play. Then, we can consider higher-level steps.
For example:
Mind that your probe circuit will load the signal -- you're adding a stub, or at least a low-value resistor (all the line impedances and terminations), messing up the amplitude, and probably the edge too. Consider adding a buffer before the probe point.
Instead of probing a clock line directly, probe a resistor or divider off it. Make a low-Z probe (450Ω into 50Ω transmission line -- or adjust as needed for other line characteristics).
Consider your needs. Do you need to check clock frequency? Perhaps a large-value resistor, or very small capacitor, would suffice to tap off the signal. Amplitude? A rectifier could be added. GPIO, a test program could set it static high/low; the test apparatus could then test its Thevenin source impedance in both states (thus avoiding a dynamic e.g. risetime test).
Limit risetime at the source. Depending on MCU, edge rate might be quite modest to begin with. Smaller or older e.g. AVR, PIC, etc. will mostly be in the several-ns range; faster/newer and lower voltage (3.3V or below) e.g. STM32, etc. can be fractional ns. Perhaps add a filter to slow the edge (good practice in general; for signals this fast, it can matter even just for on-board signals, let alone cables or probing!).
You might avoid probing high-speed lines entirely (e.g. LVDS, PCIe, etc.). Consider an alternative method, like design verification for signal quality (read: assume production is consistent), or device- or driver-level diagnostics to interrogate link quality.
To further this, you might employ alternative controls: tagging traces as impedance-controlled to the fab; checking samples from time to time; placing test traces on the PCB so you can measure its impedance more easily, without having to tap into the important traces/ports themselves (a dummy trace between two SMA connectors (normally DNP'd) for example); etc..
Consider improving signal quality of the test harness in general. Use multiple ground probes near a given high-speed signal (or signal pair). Terminate them into a PCB (use press-in or soldered pogos instead of pogos fixed in a plate), or at least collect grounds plus signal into a coax cable for better signal quality.
Use twisted pair, probably preferably with shield to nearby multiple grounds, to maintain nominal differential and common-mode impedances.
Note that twisted pair for single-ended signals is rather mediocre; you're launching a common mode Vpk/2 down the cable, which "wants" to be balanced, and some of that CM radiates away, couples with other things, etc., and grounding both ends of one wire guarantees strong reflections in the common mode, which the diff mode acts as a low-k transformer coupling into. The reflections can be absorbed in ferrite bead(s), or a differential receiver can be used to better terminate the line end (i.e., in a balanced manner).
Most of these wiring tips assume freedom to wire it as needed. Limiting things strictly to a ribbon cable, for example, has obvious drawbacks, and it's up to you whether that will affect things. You can at least reduce the impedance: typical ribbon cable is around 120Ω differential, 100Ω single-ended (G-S-G). You can roughly construct lower impedances by paralleling: a G-S-G-S-G arrangement (all G's and S's in parallel each) is... I think a hair over 50Ω? (It's not exactly half, because the two lines see each other just a bit.)
Many of these tips also incur some added cost from board-level components. If a PCB can be added above the test pins, a nearby termination resistor, or divider, etc. can be placed there, at modest expense to signal quality (the ~3cm stub of a pogo pin shouldn't be a problem for any LVCMOS signal), but the tradeoff is supporting a much longer interconnect back to the switch array / interface board / instruments. So too, any buffering you might add.
You mention that line lengths up to 30cm (a bit over 1ns electrical length) are present, and rise times down to 5ns. This sounds perfectly fine without detailed impedance controls. But you also mention that transmission line effects are evident, which seems to contradict this. Whatever the case, some of the above tips should probe useful.
