ESD knocking out PHY on device with unisolated POE

Question

I inherited this design, one problem I am having is ESD on the chassis knocks out the PHY, sometimes it can't even be reset via software. I am curious if anyone can spot any glaring errors with the schematic with respect to ESD pathways and Ethernet? Can you see anything wrong with this design?

I did attach C47 to the chassis with a zero ohm resisto (shorting C48 also made the problem worse) and it seemed to make the resetting problem worse as the unit would not pass +8kV ESD tests. The device is an POE PD device and the ethernet is one of the only ways ESD can exit the unit from the chassis.

EDIT:
Reversing the ethernet magnetics does not help the resets and doesn't seem to make a difference. Removal of C47

This is what the chassis looks like, the problem is when the aluminum case gets shocked. I have the ability to tie the chassis ground of both PCB's to the aluminium case, if I don't tie the PCB1/CPU to chassis ground I get resets, because of the location of the processor (which is close to the Aluminum case).

The arrows are points where I can tie the case to chassis ground. The problem is I need a good ESD pathway out of the device. The ethernet should be the main pathway for ESD to exit the device.

Answer 1

Can you see anything wrong with this design?

Here are my observations.

Datasheet

1. The magnetics are reverse to what is shown in the reference design.
2. Capacitors C1 to C4 do not appear in the reference design. These create a floating node on which charge can build. Without them the charge on the node equalizes with Ethernet cable.
3. C48 allows the ESD direct access to the circuit ground. The rest of the circuit that the Ethernet is servicing is not shown. There will be a path some where back to the ESD source. You should try the test without C48 open, not short.
4. The junction between C48 and C49 is also floating unless the chassis is connected to power earth. If the whole circuit is floating, then a resistor (say 1MΩ) across C48, to allow the chassis voltage to equalize with the circuit ground voltage, may be advised.

This kind of problem is often caused by the ground rising above input/supply voltages causing internal latch-up as per absolute maximum ratings. This kind of latch-up can only be resolved by power-down reset. Using diode clamps on all the signal/power inputs may help understand or solve the problem. Clearly this ESD event bypasses all existing protection mechanisms.

Answer 2

Can you share a picture or diagram of the layout and test setup?

Often times ESD problems are not necessarily schematic problems, but rather layout problems. The current from the ESD gun is looking for the lowest impedance path back to the source. If this happens to be through your circuit this can be bad! This can often be remedied easily once the current path is understood, but where the ESD is applied and where the return wire are connected will be important in determining what is happening.

Another possible failure mechanism can be field coupling from the ESD spike I to your circuit, but this again requires understanding the current path and knowing the layout.

That aside, assuming the current is coming in on the Ethernet lines themselves adding TVS protection in your schematic could go a long way to solving your issues. Placing a TVS from each line to chassis near the connector would shunt the energy back to the chassis and avoid any issues.

Answer 3

Ground early and often.

It sounds like there are no other outside connections from the equipment, so it can be grounded to itself for EMI purposes, and, the galvanic situation doesn't really matter.

It could be a double-insulated system, then, or single-insulated with a grounded enclosure. Given the ground wire, it seems the latter case has been chosen; I would also recommend this, as it simplifies design.

It also doesn't seem that there are any sensitive or high-power circuits within, that might make ground-loop problems.

But do realize I am making a great many assumptions already, due to the drought of supplied information.

Consider these steps:

0. Tie all standoffs/spacers to circuit ground plane and enclosure. This includes all orange horizontal blob/arrow sections (and, for that matter, as much of the front as is feasible, except for minimal openings for displays/indicators, keypad, etc.).
1. Use a bulkhead Ethernet receptacle to ensure EMI shielding to the enclosure. This will have to be a type that includes magnetics and PoE taps.
2. Preferably, add EMI finger strip around the outermost board(s) to close the top of the enclosure, making a six-sided box for EMI purposes.
3. I notice these are drawn as gaps; in case this is true, add bonding via EMI strip for any enclosure segments as well.

A gap length of just 2-3" (5-7cm) is enough to let significant ESD through. Place EMI strip, standoffs, etc. accordingly.

Since aluminum is indicated, mind that anodization (if applicable) must be sanded off to make EMI contact with bare metal. If needed for corrosion resistance, a conductive Alodine/chromate process is recommended. Mask contact surfaces before painting.

Preferably, PCB2 and PCB1 would switch places, so that PCB2 can be anchored to the enclosure first, allowing a vertical board-mount connector to be used instead of a bulkhead adaptor and awkward wiring. (Probably, a bulkhead magnetics connector doesn't exist (for good reason), and a small PCB would have to be made, with a minimal length ribbon or flex cable joining it to the PHY proper. TVSs can also be placed on said board.)

If Other PCB cannot be anchored to the stack with conductive standoffs/spacers, it must be treated as an external connection: many grounds in the connecting cable, or preferably shielding; filtering, ESD protection, etc. on all signals; differential signaling with wide CMR where higher speeds are required.

Note that PHY chip, MII routing, PCB layout, mechanical drawings, etc. were not included in the question, so a conclusive answer is impossible. Perhaps the above will improve things, but it might also make things worse. I'm afraid there are too many variables left undefined to make a conclusive determination.

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For readers' interest, some closing comments on EMC questions:

• EMC is a holistic subject. There is no detail too small to leave out, and the scope is always much, much broader than anyone expects. (I have seen few exceptions in my time here; as you can surmise, this is not among them.)
• Details matter. If you are unable to provide all possible details, say for IP reasons (includes potential employment concerns!), I would encourage locating a local expert who can assist your project at a reasonable fee.
  • By extension, essentially any well-enough described project posted to Stack becomes open-source hardware by definition; if you aren't willing or able to provide such a license to your IP, the business alternative is required.
• For my part at least, the only way I can be confident answering an EMC question, is to have the equipment in hand, with a well-defined test setup, and equipment ready to measure and modify it. Anything less is subject to error.
• The error margins, due to omitted information, grow wildly with the amount of information missing. The typical case might diverge fairly slowly, but "typical" is informed by assumptions drawn from traditional design practices. The less that gets specifically called out in the schematic, layout, etc., the worse the worst-case conclusion will be. It is impossible to provide any confidence in such an answer -- perhaps one strains to even call it an "answer" under the rules of this site!
• Conversely, the output of such a study, will be extremely focused: one specific set of changes, for that particular item and test setup, to achieve some well-defined set of goals (immunity/emissions levels, say). Those changes probably won't be of much general use elsewhere; every case is different.
• Likewise, I would encourage readers to employ extreme skepticism towards any clear-cut answer on EMC. Anyone giving a conclusive answer, on more than a trivial topic, is at best, almost certainly wrong; at worst, actively trying to mislead you. Answers that provide reasoning and guidance for you to derive the answer yourself, may be more authoritative; but on a topic as complex as EMC, sufficient explanation quickly balloons to book length; it's hard to justify the effort spent writing them.
• Finally, the lack of information tends to foster back-and-forth conversations in comments, or even post-editing (as has already happened here). For these reasons, I would generally discourage asking general EMC questions on Stack; it's simply not a topic suited to the restrictive format. Highly limited, simple, well-described questions can be okay still, but practical "this is my thing, what's wrong with it" questions take on many of these problems. For more discussion-oriented questions, I would just recommend a general forum format such as EEVblog.

(Para-meta comment: as there is no such thing as a "sticky" post on Stack topics, addenda to posts seems the most reasonable and visible method to convey these concerns to readers.) (Also, this disclaimer is almost longer than the relevant post content itself, which goes to show the complexity of the subject while still trying to explain it clearly.)