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I'm working on two PMOS PWM circuits and need some help understanding the differences and functionalities of each. The goal is to achieve better wave transients for a PWM signal generated by a 3.3V MCU and shifted to a separately supplied counter IC with 3V VCC and -3V VSS. I've attached an image of the circuits for reference.

Schematic for both options

Circuit A:

Q2 PMOS with source connected to VCC and drain connected to VSS through a 1K resistor (R4). The gate is driven by the PWM input. The PWM output is taken from a 100K resistor (R5).

Circuit B: (Level Shifter Approach)

Q1 PMOS with source connected to GND and drain connected to VSS through a 1K resistor (R1). The gate is driven by the PWM input. The PWM output is taken from a 100K resistor (R3). I'm trying to understand:

  1. The functional differences between these two circuits.
  2. The potential use cases for each configuration.
  3. How the placement of the PMOS transistor and the resistors impacts the behavior of the PWM signal.
  4. How Circuit B functions as a level shifter to improve wave transients for a PWM signal created by a 3.3V MCU and shifted to a -3V VSS.

Any insights or explanations would be greatly appreciated!

Thanks!

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  • \$\begingroup\$ Do you care if the PWM output signal is inverted vs. the input? What exactly is a "wave transient" and why does it need improvement? \$\endgroup\$
    – John D
    Commented May 16 at 18:08
  • \$\begingroup\$ I mainly concern about the turn-on and turn-off times of the PWM signal. As you point out, signal inversion can be considered as another aspect. Improving the wave transients refers to capability of opting for higher frequency designs. \$\endgroup\$
    – Fatihy
    Commented May 16 at 18:26
  • \$\begingroup\$ Why not show simulation results? Have you considered using a simulator? Most engineers are using them now. \$\endgroup\$
    – Andy aka
    Commented May 16 at 19:00

1 Answer 1

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The main difference between ckt A & ckt B is the source of the current that drives the 1k load resistor. For A, the source is the power supply node, Vcc. However, for B it is the input node, PWM_in. Ckt B will draw far more current & power from the input signal than ckt A.

Hence, the speed of ckt B will be far more dependant upon the electrical properties of the input node than ckt A.

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    \$\begingroup\$ Also depending on node capacitance, the 1 K pull-down and the 100 K series resistor will have a significant detrimental (and asymmetrical) effect on rise and fall times. \$\endgroup\$
    – John D
    Commented May 16 at 20:54

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