Troubleshooting Voltage Sensing Issues in Buck-Boost Chip Simulations

Question

I performed a simulation on a buck-boost chip (LT8390). I understand that the sensing resistor placed between LSP and LSN is supposed to sense the differential voltage. This voltage is then amplified and compared with the feedback voltage. The maximum current sense threshold is 50 mV in both peak-buck and peak-boost modes (datasheet page 19).

When I ran my simulation (input = 24 V, output = 20 V, maximum I = 8 A), I did not observe a reasonable voltage difference between LSP and LSN. I did not expect the voltage to increase to 50 mV. Other signals, such as switching, appear correct; the only issue is with this differential voltage signal.

I downloaded two simulations from LT. One follows the rule and never exceeds 50 mV. The second one exceeds the voltage but not to the extent of my design, which reaches 0.4 V at the start for a light load. And if I decrease the load, the LSP/LSN voltage falls within the expected range.

My question: Does my simulation indicate a bad design? How can I fix this issue?

Adding current sensing image and VLSP-VLSN at the same time:

Added a zoomed-out image with VLSN-VLSP sensed directly from the chip.

Answer 1

The spikes you're seeing there are from transient current caused by parasitic capacitance charging and discharging when the MOSFETs switch. If you overlay the SW1 and SW2 traces on top of the LSP/LSN trace, you'll see that the spikes coincide exactly with the edges of the SW nodes.

Also, if you check the voltage at the actual LSP/LSN pins of the IC, you'll see that C18 eliminates those spikes almost entirely (which is the entire purpose of that cap and its associated resistors).

There's nothing wrong with the circuit.