design strategy of a pulse delay line between two components

Question

There are two components 74ABT04D Hex inverter and UCC5304DWVR gate driver. 74ABT04D Hex inverter is the signal genrator UCC5304DWVR is the reciever of the delayed signal. I know that my delay line has to be matched.Given the datasheet below what source and load I need to put for my delay line? THanks. https://www.mouser.co.il/datasheet/2/916/74ABT04-1541721.pdf https://www.ti.com/lit/ds/symlink/ucc5304.pdf?ts=1715329802200&ref_url=https%253A%252F%252Fwww.mouser.co.il%252F

Answer 1

A single section of LC delay line needs to be terminated in a resistor of value \$\sqrt{\frac{L}{C}}\$: -

The one above is for 50 Ω i.e. \$\sqrt{\frac{L}{C}}\$ = 50 Ω.

It can also be proven that for a decent range of frequencies (from DC up to a high frequency point), the input impedance will also be \$\sqrt{\frac{L}{C}}\$. The point where it starts to unravel is about one-tenth of the resonant frequency formed by L and C. In the example above, that will be one-tenth of 31.8 MHz.

This means that if you want a decent delay line, you choose the resonant frequency to be about ten times higher than your maximum frequency (including relevant square wave harmonics).

How much delay comes from a single L and C? If I plot the phase response of the output from low frequencies up to (say) 1 MHz I get this: -

In other words, the phase increases linearly with frequency and, this equals a constant time delay. In the example above it 5 ns (\$\sqrt{L\cdot C}\$). At around one tenth of the resonant frequency (around 3.18 MHz) it starts to be a little non-linear in delay so, be aware of what values to pick.

And, of course, the LC section has the same input and output impedance so, multiple sections can be cascaded with a single terminator right at the end of the final section.

Images and some text taken from an answer I gave on Codidact

However I am not sure what source and load to use by the datasheets of the components when I design this LC ladder in LTSPICE.

You have options. Either terminate in a value as per the formula above or use a series terminator in the source of the same value (taking into account that your driving source my be circa 15 Ω. Series source termination example: -

The theoretical delay should be 20 ns but, it's more like 21 ns due to the higher-than-anticipated BW of the signal input (100 ns rise and fall times).