Fig. 3.33, page 62 from Fundamentals of Power Electronics 3rd edition by Robert W. Erickson and Dragan Maksimovic
If we assume the transistor is in conduction mode and the inductor has parasitic resistance \$R_L\$, applying KVL clock-wise we would get
$$ V_{batt} - I_LR_L - V_L = 0 \Rightarrow V_L = V_{batt} - I_LR_L $$
When the transistor is in cut-off mode, we apply KVL in the second circuit, that is:
$$ -V_L + I_LR_L + V_D + V = 0 \Rightarrow V_L = I_LR_L + V_D + V $$
When we use volts-seconds balance, the part of the relation that contains the inductor current for interval \$DT\$ and \$(1-D)T\$ will yield
$$ -I_LR_LD+I_LR_L(1-D) =I_LR_L(1 - 2D) $$
This seems to be wrong because there is no \$(1 - 2D)\$ in the final relation \$V(D)\$. The final relation assumes that the polarity of the inductor doesn't reverse, which would result in:
$$ V_L + I_LR_L + V_D = V \Rightarrow V_L = -I_LR_L - V_D + V $$
The part which contains \$I_L\$ now being
$$ -I_LR_LD-I_LR_L(1-D) =-I_LR_L $$
Using the assumption that the inductor's polarity doesn't reverse, I can get to the right relation between \$V_{batt}\$ and \$V\$, but why do we assume that it doesn't reverse? The inductor has to be in series with the battery, such that
$$ V_{batt} + V_L - I_LR_L \ge V_x - V_D $$
Where \$V_x\$ is the voltage at the top rail, but using the assumption that the polarity doesn't reverse, then
$$ V_{batt} - V_L - I_LR_L\ge V_x - V_D $$
This can't be since the current through the inductor is decreasing, hence its polarity will reverse. Why is it assumed that it is not reversed? Is this assumption only valid in this context, that is an ideal world, because the battery is connected to the terminal of the inductor so it keeps its polarity fixed?
When we use volts-seconds balance, the part of the relation that contains the inductor current for interval DT and (1−D)T will yield
why? Why do you take those parts only? Volt-second balance is the magnetisation balance. You need to use the full inductor voltage. \$\endgroup\$