Filter design according to harmonics in an inverter

Question

According to the Fourier series, when AC waves of different frequencies are added to the fundamental frequency, we can obtain waves such as square and sawtooth. When we filter out the harmonics in this square or another wave, we can access the AC wave at the frequency we want to reach.

Below is an inverter output generated from SPWM and switched in the full bridge. I want to convert this to a sine wave using an LC filter.

Let's say my switching frequency is 50 kHz. I want my output to be 50 Hz using an LC filter, but I don't know how I should choose the L and C values. In articles, the cut-off frequency is generally at kHz levels, for example 5 kHz, 3 kHz.

An LC low pass filter with a cut-off frequency of 5 kHz means that it will not pass harmonics above 5kHz. If it passes frequencies below 5 kHz, I cannot understand how the output is 50 Hz.

Secondly, by which formula and on what basis should I choose the L and C values? In some articles, the voltage drop at the output is taken into account, in some articles it is done by calculating harmonic percentages. What is the correct method?

Considering the Fourier series theory, I am trying to understand how harmonics are eliminated, how to get 50 Hz output even though the cutoff frequency is very high, and how L and C values should be selected.

Source: my own study

Answer 1

A few guidelines: -

• You don't want your filter to be resonant close to 50 Hz or you will get bad problems
• You don't want your filter to be resonant close to 50 kHz (the switching frequency) or you will get bad problems
• Choose the resonant frequency to be round about the geometric mean i.e. \$\sqrt{50\cdot 50000} \approx 1600 Hz\$
• Resonant frequency formula: \$f = \dfrac{1}{2\pi\sqrt{LC}}\$
• Try and keep the q-factor low under no load conditions to prevent unwanted (and usually serious) ringing
• Lowering the q-factor usually means increasing C and decreasing L by the same amount
• Use a simulator (clearly you have one) and test under light and full load power conditions
• Expect to increase the resonant frequency a little bit to get an improved solution
• Don't expect a really-good 50 Hz sinewave out without additional LC filtering

If it passes frequencies below 5Khz, I cannot understand how the output is 50 Hz

Your PWM frequency is 50 kHz and cannot contain harmonics lower than 50 kHz and that means the only other frequency present is 50 Hz. Here's an example: -

I've created an SPWM waveform in red and I've low-pass filtered it at 16 kHz. As you can see there are still a lot of PWM artefacts showing. L was 100 μH and C was 2 μF. If I make the filter have a lower cut-off: -

This time I've increased L to 1 mH (a cut-off of 5 kHz) and the ripple from the PWM artefacts has reduced a lot but, it's still present in sufficient quantities to cause EMI disturbances.

So, you choose the filter inductance and capacitance to suit what your EMI requirements are. And, finally, please do use a simulator and take into account winding resistances and full (and off) load currents.

Answer 2

There are several constraints missing:

• Allowed output level / emissions at various frequencies (Fsw, harmonics)
• Maximum output impedance at signal frequency; output regulation
• Acceptable component cost, size, space, losses, etc.

To minimize Zout, we must minimize series impedance between inverter and load. This dictates Fc as high as possible (close to, but still below, Fsw).

That is, notice that a filter isn't simply "pass or cut", it's by degree, and for frequencies near Fc (cutoff frequency), signals are not just modified in terms of amplitude, but the source impedance is affected by the filter as well. We want Fc far enough above the signal frequency that its impedance remains low, and therefore regulation (change in Vout for change in Iload) remains acceptable.

Alternately, this dictates low Zo of the filter (so that L will be small and C large), but this may be frowned upon, or prohibited outright, by transient behavior: peak startup current from the inverter, or short-circuit discharge current to the output. (Though I'm not sure anyone would really care about short-circuit current for a mains inverter. It can be important for general power supply applications.) Large C also consumes reactive power at the signal frequency, which generally costs efficiency in a mains inverter, and in the extreme case, wastes inverter capacity (apparent power, VAs).

Or as a final alternative, we employ a more complicated control circuit that adjusts for output voltage (closed loop control, whether tracking the waveform as a proper feedback amplifier, or servoing the amplitude to keep it stable).

To get desired emissions, we must set Fc at least somewhat lower than Fsw, and filter order high enough, to get sufficient attenuation. For example, if allowed output is 1mV at 10MHz, the inverter delivers 200V, and it's at the 10MHz/50kHz = 500th harmonic, which for a square wave is 1/500th the fundamental amplitude, or ballpark 400mV, so we require at least (400mV)/(1mV) = 400x, or 52dB, of attenuation between inverter and output at 10MHz. And so on for other frequencies of interest. Probably, getting Fsw itself down to some 100s or 10s of mV is the primary goal, and harmonics fall trivially after that, but some frequencies/bands may end up peaked due to component parasitics and layout, and this can necessitate revisions, including adding a high-frequency filter.

To minimize component size, we also prefer a high Fc. Since L and C are both inversely proportional to Fc, while component volume is more or less proportional to value.

Filter order is an open question. We might further optimize for minimum energy storage -- which further minimizes component volume -- and choose accordingly. For example, if 40dB attenuation is required at Fsw, and asymptotic attenuation goes as 20dB/dec/order, then we need Fc one decade below Fsw for a 2nd order filter (simple LC), 1/2 decade (about a third) for 4th, etc. As order goes up, Fc changes less (approaches Fsw), while the number of components (of approximately equal sizes) is proportional to order. It turns out, this tradeoff balances at about \$n = \ln A\$, for attenuation ratio A and filter order n. That is, if we need 40dB or 100x attenuation, a filter order around 4.6 will minimize component size.

Finally, filter type is dictated by two factors: 1. The inverter must have an inductive load, otherwise switching loss is increased at least some (resistive load, all harmonics dissipated as heat), or wildly so (capacitive load, switching incurs huge peak switching currents). So we must have an inductor-input type lowpass filter. 2. Capacitors are cheaper and more compact than inductors, so we prefer increasing filter order one more step, to maximize capacitor count. Combined with the L-input constraint, we shall choose filters of even order. So we would choose \$n = 4\$ for the above case, and adjust Fc a little bit lower than ideal to account for the order not being the exact fraction calculated.

One final detail, not evident from the above, but separately: a filter only performs to design specs when terminated into at least one resistance. The inverter is an extremely low resistance, bordering on a short circuit. The load/output may be a completely open circuit (unplugged), or it may be inductive or capacitive loads (motors, SMPSs...). (It could even be a short circuit, which we should design for from a system protection standpoint, but wouldn't be expected to pass emissions under.) How do we resolve these requirements? Two ways: 1. choose a constant-output-resistance filter, or diplexing filter; 2. add a snubber network. ((2) can also be seen as a crude subset of (1).) I won't go into detail about CR or diplexing filters, but the snubber is simple, and suitable for this case. Simply connect an R+C in shunt at the output, of value R = Zo (of the filter), and C > 2.5 C_total (that is, much greater than the total capacitance in the filter). This doesn't work so well into a capacitive load (where the load adds to the total), and if we desired to account for capacitive or low-impedance loads as well, a series R||L network must be added. (Usually, this won't be considered an important use-case, and, again, inductors are relatively expensive and bulky components, so we'd prefer to mitigate it with R+Cs where we can.)

Also note that, if this is a push-pull or H-bridge application, consider each output channel as stand-alone with respect to circuit ground: you need one filter each. Providing DM and CM filtering independently, isn't very practical, and simply filtering each in the normal mode is simplest. I would allow that, a lower order 1st-pass normal mode filter might be used, and then DM and CM can be treated separately -- the optimization being that, DM emissions may be more tolerable than CM emissions, so a pair of NM filters followed by a CMC or two might offer adequate filtering. (But it probably won't be adequate for a grid-tied inverter, where emissions from each port must meet limits, not just their combined CM emissions.)