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There are two circuits where one stage output is supposed to be the input of the other stage. Both circuits act properly where as you can see the output of the first stage is almost the same as the input of the second stage. When I combine them together I expect to see the output of the second stage. However as shown in the combined circuit, I don't get from the second stage the output as before. What could be done to expected good signal I was getting from the second stage when it was stand alone? Thanks. enter image description here

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  • \$\begingroup\$ Q1 appears upside down. Nevermind, negative voltage on top. \$\endgroup\$
    – winny
    Commented Apr 10 at 7:33
  • \$\begingroup\$ You tested the upper circuit with a voltage source as an input, which by definition has zero impedance. However, the output of the lower circuit is not anywhere close to a voltage source -- it has significant output impedance. \$\endgroup\$
    – Dave Tweed
    Commented Apr 10 at 11:41
  • \$\begingroup\$ Hello Mr.Tweed, how do I fix this impedance mismatch? Thanks. \$\endgroup\$
    – Chris95
    Commented Apr 10 at 11:52
  • \$\begingroup\$ Instead of diving straight into fixing the low-level details of your model, please describe the application. What are the actual input and output of the overall circuit, and what are you trying to accomplish? \$\endgroup\$
    – Dave Tweed
    Commented Apr 10 at 13:02
  • \$\begingroup\$ Hello Mr.Tweed i am trying to copy a lab circuit into a simulation model.basickly its a part of a circuit which shapes a pulse for power amplifier gate. How do uou reccomend me using LTSPICE to match between these stages? \$\endgroup\$
    – Chris95
    Commented Apr 10 at 16:01

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