Clarification about leakage current in IC

Question

Datasheets usually specific pin leakage current for digital inputs in the Electrical Characteristics, which is generally in microamperes (µA) range. I understood from different SE posts that the specified current is usually much higher than the actual leakage current. I also understand that the leakage current direction depends on the voltage applied.

Here are a couple different examples mentioning leakage current limits in different ways.

Img Src: Micron DDR5 SDRAM Datasheet

Img Src: TI TPS51200-EP Datasheet

My general question is: Which of the following is true for the "input leakage current" specification of a digital input pin in the datasheet?

1. Is it the maximum leakage current the pin will draw when a voltage is applied to it?
2. Is it the maximum leakage current that must be allowed for an applied voltage?

The reason I ask this is because if were to pull up a pin with a resistor to a voltage, there would be a voltage drop across the resistor due to the leakage current that flows through the resistor. So, for example, an EN input has 10 µA maximum leakage current and I connect it to 1.8 V via a 100 kΩ pullup resistor, that would cause a drop of 1 V across the resistor in the worst case and the EN pin would not detect it as HIGH since it would see only 0.8 V whereas the VIH could be, for example, 1.2 V minimum.

So, if #2 would be true, we would need to connect a resistor of 1.8 V/10 µA = 180 kΩ, which would then violate the VIH specification in case a leakage current close to 10 µA flows into the pin. And conversely if I connect a lower value resistor such that VIH is met, which makes sense, it would mean a higher leakage current could flow.

Am I misunderstanding anything here? Could someone please clarify this for me?

EDIT: Summary of what I wanted to clarify and have understood based on the answers/comments. Hope it is correct: Basically, the leakage current is not something that can be or needs to be limited externally and only the maximum specified leakage current will flow for an applied voltage virtually irrespective of the external pull-up/down resistor value. Any external pull-up/down resistors should be sized such that VIH/VIL is not violated for the maximum leakage current that can flow through those resistors.

Answer 1

The datasheet specifies a maximum +XμA, and a minimum of -YμA. If that's what the datasheet says, then you can trust it, unless the device is damaged, or being used in some unconventional manner, unsupported by the manufacturer.

It's true that leakage current magnitude and direction can and will change depending on pin potential.

I've always assumed that (unless otherwise noted) if the datasheet gives a single, positive figure for maximum leakage current, say \$I\$, then \$-I\$ could also flow.

You are correct when you say that a resistor in series with the input will develop a potential difference in proportion to that leakage current, and that will affect the potential actually seen at the pin itself. Using a lower resistance in order to mitigate this, may result in more leakage current, but that is not necessarily always the case. Leakage current is unlikely to have an ohmic relationship with applied potential.

A couple of examples:

^{simulate this circuit – Schematic created using CircuitLab}

This certainly can cause input potential to lie inside the range \$V_{IL}\$ to \$V_{IH}\$, which is an indeterminate condition, and you are right to be concerned by it.

While my next point has nothing to do with leakage current, it is also worthy of note: having a resistance in the path of input current will slow signal slew rate, due to input capacitance. Using an excessively large pull-up or pull-down resistor can be very detrimental:

^{simulate this circuit}

Q1 represents an open-drain output from something or other, usually requiring a pull-up resistor. The transistor is switched on and off by input X, which here is a square wave at 10kHz:

The signal at the drain, which is the IC's input Y, looks like this:

The transistor is able to pull Y down to 0V, by discharging input capacitance C1 very rapidly through its low on-resistance, but the rising edges are really slow. We have to rely on current severely limited by R1 to charge that capacitor up to +5V. That might not be a problem in many applications, but if you have the need for speed, then resistance is very problematic.

The time it takes for the capacitor to charge to 63% of "full" (5V) is the time-constant \$\tau\$:

$$ \tau=R_1C_1 $$

Obviously, a smaller resistance is beneficial here too, which makes two good reasons for using as small a resistance as possible, while still complying with other requirements, such as circuit power consumption.

Answer 2

1. Is it the maximum leakage current the pin will draw when a voltage is applied to it?

Yes. Input leakage current in CMOS devices represents the current that can flow into or out of the pin when a voltage is present there.

The leakage currents, quite possibly, come from either the input transistors or the protection diodes (if any) or both.

For RESET_n pin of the DDR5 SDRAM, for example, assuming the input has protection diodes tied to both rails (not mentioned in the datasheet but let's assume for a moment), if the input voltage is at 0V then the high-side diode will be reverse biased so the leakage current will flow out of the pin, hence the negative sign. Likewise, when the input voltage is at a higher level then the low-side diode will be reverse biased so the leakage current will flow into the pin, hence the positive sign.

The logic inputs, despite the FETs have high input impedances, may still draw some non-zero leakage currents. Apart from that, the internal pull-ups/pull-downs will bring extra leakages. A good example is shown in the DDR5 SDRAM datasheet: If you check the Table 274 you'll notice that some logic inputs have extra leakages due to the weak pull-ups/pull-downs.

So, for example, an EN input has 10 µA maximum leakage current and I connect it to 1.8 V via a 100 kΩ pullup resistor, that would cause a drop of 1 V across the resistor in the worst case and the EN pin would not detect it as HIGH since it would see only 0.8 V whereas the VIH could be, for example, 1.2 V minimum.

Then you shouldn't use that high pull-up. For any external pull-ups/pull-downs that you'll connect, take the leakages into account and use suitable values not to violate the input voltage range requirements (V_IL & V_IH).

Answer 3

You have two different values for two different pins.

And you must calculate the resistor so that it still exceeds any logic threshold you want.

If you need a pull-up to 1.8V, and must be above 1.7V, you have 0.1V allowed drop over resistor at any leakage current. 0.1V / 10uA is 10 kohms.

So yes,

1. for any applied voltage there could be max leakage current going into or out of chip. This includes applying 0V.
2. It makes sense yes to assume at any applied voltage the pin could leak the maximum leakage current.

Which means, if you intend to connect 1000 pins on same bus, each with leakage of 1uA max, your output needs to be strong enough to be able to drive 1mA in theory while making sure the voltage on bus is within logic level margins.