Tie all unused GPIO to GND?

Question

Recently, during a discussion with a senior electronics engineer on an industrial project that operates at 48V and is housed within a metallic casing, a point of contention arose regarding ESD compliance. The engineer argued that for ESD compliance, particularly in the rail industry where high-voltage disturbances are a concern, it is a standard practice to connect all unused GPIO pins of the MCU to ground through resistors. This method is believed to mitigate the risk of damage to the MCU from high-voltage perturbations via bounding.

Here is a diagram illustrating the proposed setup:

From my experience, I have never encountered this practice and questioned its necessity, especially in a system operating at a relatively low voltage and with the PCB already grounded through planes on both the top and bottom layers.

Is this grounding solution indeed relevant and necessary for ESD compliance in such a context?

Answer 1

The PIC24FJ64GA004 Datasheet specifies the general practice for unused I/Os:

2.8 Unused I/Os

Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10 kΩ resistor to VSS on unused pins and drive the output to logic low.

Answer 2

Apart from the valid reasons given in answers, if you are developing a circuit board, it's always useful to have spare IO brought out to a small but convenient test point just in case you suddenly find that you have overlooked something and need that extra IO.

The fact that there might be a resistor pulling it to GND or Vcc is not a big deal at all. However, what can be a big deal is cutting tracks and making a right mess of things.

Give yourself some future-proofing.

Answer 3

It might be relevant, but it depends.

And you already talk about two scenarios, you mention tying unused IO pins to ground (without mentioning any resistors so reader may assume direct connection), and then show another case where unused IO pins are tied to ground via 1k resistors.

In general, floating IO pins may be assumed as bad practice.

But, some MCUs don't even enable them as digital inputs, so the input pins that are floating are irrelevant.

However, some MCUs that always keep them as digital inputs, floating voltages can cause excess current consumption. And it is very bad if your MCU accidentally uses data from floating input for some purpose, as it is random.

The obvious choises are to enable internal pull resistors, up or down.

While most MCUs have at least internal pull-ups, not all MCUs have them, and even if they do, they are only enabled when the software runs. So when the software has not yet turned them on, the pins float.

Another option is to turn the pins as outputs. But that also only works when MCU runs and has initialized the pins.

One option is to simply short all unused pins to ground directly. While good, some programmer may have made an error and the pin is set as high output. Or you must use a factory bootloader that uses multiple different interfaces to outputs even if your program does not need the pins.

Some MCU datasheets do recommend 1k to pins that are exposed to noise, with that being specified as PCB track longer than 50mm.

So depending on your scenario it might make sense to use 1k resistors on all unused pins. But it is also in a metal case and only EMI would come through holes in the case (for connectors and wires) and through the wires connected to the board. In an industrial/automotive setting, you might want to take EMI seriously.

Answer 4

It is generally good practice to tie unused GPIO (CMOS) inputs to ground, and outputs to ground or vcc through some resistor value that would otherwise not cause excessive pin currents beyond rated specifications. In the case he mentioned 1K which seems like a good value to keep GPIO currents < 3.3mA assuming Vcc=3.3V.

Answer 5

Look at Microchip's AN1416 app note: https://ww1.microchip.com/downloads/en/Appnotes/90001416a.pdf#page=15 under Hardware Design.

Unused Port Pins

By default, PIC microcontroller I/O pins power up as inputs. A digital input pin consumes the least amount of power when the input voltage is near VDD or VSS. If the input is at some voltage between VDD and VSS, the transistors inside the digital input buffer are biased in the linear region and they will consume a significant amount of current. On an unused I/O pin, which is left floating, the voltage on the pin can drift to VDD/2 or oscillate, causing the unused I/O pin to consume signif- icant power. The I/O pin can use as much as 100 μA if a switching signal is coupled onto the pin.

An unused I/O pin should be left unconnected, but con- figured as an output pin, driving to either state (high or low), or configured as an input with an external resistor (about 10 kΩ) pulling it to VDD or VSS. If such a pin can be configured as an analog input, the digital input buffer is turned off, preventing the excess current consump- tion caused by a floating signal. Any of these methods will prevent the floating node case, minimizing power.

Analog Inputs

Analog inputs have a very high impedance so they con- sume very little current. They will consume less current than a digital input if the applied voltage would normally be centered between VDD and VSS. Sometimes, it is appropriate and possible to configure digital inputs as analog inputs when the digital input must go to a low-power state.

Digital Inputs and Outputs

As long as a digital input is pulled to VDD or VSS, only the pin input leakage current will be consumed.

There is no additional current consumed by a digital output pin, other than the current going through the pin to power the external circuit. Close attention should be paid to the external circuits to ensure that the output is being driven to the state which causes the lowest power consumption. If an external circuit is powered down, make sure that any I/O pin connected to it is driven low to prevent sinking current through the disabled circuit.

For digital inputs and outputs with high switching frequencies, make sure that there is no stray capacitance on the bus by minimizing trace length and eliminating unnecessary components.

Not enough experience to comment too much, other than it sounds like using the analog mode is the best if power is your primary concern and output mode driven low if your primary concern is EMI. This can sometimes be challenging when routing so many pins close to each other especially since they are essentially useless. Looking at the diagram though, it does seem this chip is way overkill if you have that many unused io pins. If this is designed to be modified later, then you probably should route them now to something, although it is not impossible to solder to individual pins that only have pads without tracks.

Answer 6

Setting all the unused gpio as outputs and typing to ground (can use 0 ohm resistors if the design is mature and firmware is stable) also has the benefit of lowering the IC's ground impedance which is always a good thing. It can help with EMC and signal integrity amongst other things.

Answer 7

I'm late to the party, but I want to provide some additional comments. It's helpful when considering ESD and EMI effects to go back to the basics of circuit analysis or maybe even electromagnetics.

Let's consider the case where your electronics are in an enclosed metal chassis. Suppose there's a large potential voltage between the chassis and some other device. In that case, the potential will equalize when the device or material is close enough to contact the chassis or create a dielectric breakdown (arc). Then the electrons on the surface of one of the devices will flow to the other to evenly distribute the charges. This flow of charges can be measured as a current, and the current will generate a voltage across segments of the chassis that is related to the resistance (or conductance) of the enclosure. Higher currents and/or higher resistance means more power dissipation and more heating.

If for some reason, the resistive path through your electronics is lower or on the same order as your enclosure, the current will flow through your electronics. This can be avoided, however, if you only connect your electronics to the chassis at a single point. This way, fault currents on the chassis cannot flow through the electronics. We call this a single-point grounding scheme (SPG). Using SPG is very common in high-reliability applications such as industrial or aerospace settings for this exact reason. I won't go into this now, but it's important to know that SPG is not the best grounding scheme for all applications.

For your application, if your device is in a conductive enclosure, and has an SPG, your ESD concern should already be pretty low. However, ESD is not the only thing you should be considering when it comes to the safety of your electronics. Industrial environments are notorious for high EMI, including low-frequency fields generated by motors, generators, etc. These low-frequency fields can penetrate your enclosure and interact with your electronics.

If your MCU inputs are floating, any EMI on the pins can adjust the voltage to create spurious signals that could cause unexpected behavior, or even worse, damage. This is a bad idea.

If your MCU inputs are tied directly to ground, these spurious signals cannot change the signal on those pins relative to ground, and your inputs and software functionality are safe. However, if your software/firmware is not yet tested, these inputs could accidentally be configured as outputs and driven to levels that may cause damage if there is no other fault protection. Such faults could also be a concern in environments where single-event upsets are a problem (e.g. a bit flip in the control register for an unused pin set the pin to an output high level). This could be a problem whether you intend to configure these pins as an input or an output driven low.

If your MCU leaves these pins as floating inputs with an internal pull-up or pull-down, EMI is not likely to have any effect on them when the board is powered on and running, but you will want to pay attention to the reset state of these pins. When your device is in reset, the I/O may be configured differently than you've programmed.

The overall safest method for terminating unused I/O then is to tie each pin to a resistor to ground and drive the pin as an output low. This protects against EMI and fault conditions in all cases we've discussed here. If the resistor is large enough, you shouldn't see much power consumption, even during fault conditions. If the resistor is too large, the EMI can still couple to the pin and the charge on the pin may accumulate faster than it flows through the resistor, still causing unwanted behavior.

There's a trade-off here that needs to be made, and you should do your homework to ensure you make the right choice. No solution works best for everything. The resistor pull-down may be the safest, but it's not the lowest power, and it's not the most cost/space efficient. Most other methods are safe enough most of the time. What if you have 100 unused I/O? Should you tie each pin to a resistor to ground? As with almost every question I get related to EMC, the answer is "it depends!"