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I want to design an SD card to Memory Stick adapter. I will need to somehow implement SD controller (host) and Memory Stick controller (device) in my design, then do the translation between the commands.

On this page I have found a photo of the internals of a commercial adapter. Cropped version:

Commercial SD to Memory Stick adapter

There are two ICs on the PCB: a QFN38 marked as SD003AC H31223 0822 S7C (I couldn't find any info about it, might be an ASIC) and a TSSOP8 which looks like it holds the firmware for the first chip. Am I reading the markings correctly? What is the function of these two ICs?

Cropped and rotated close up of the main IC:

Cropped and rotated close up of the main IC

A very similar looking QFN38 chip can be found in various SD cards and Memory Stick devices, but it's possible that it's just the same package and the IC inside is different.

I started designin such adapter myself, the PCB seems pretty simple, but the QFN38 chip needs to be replaced with something performing similar function. What are the available options?

So far, this is my design (replica) of the board in the photo:

KiCad design of SD to Memory Stick adapter

What should be the next step in making this adapter?

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    \$\begingroup\$ IIRC passive in SPI mode. active otherwise. \$\endgroup\$
    – Behrooz
    Commented Mar 4 at 10:04
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    \$\begingroup\$ @Behrooz I have never heard of an SPI mode for memory sticks? Pretty sure that doesn't exist! \$\endgroup\$
    – Marcus Müller
    Commented Mar 4 at 11:20
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    \$\begingroup\$ @MarcusMüller You're right. only sd has spi. sony used an spi-like protocol in older memory implementations. but i found no docs for mem stick duo using spi. \$\endgroup\$
    – Behrooz
    Commented Mar 5 at 13:52

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The Sony Memory Stick interface state machine seems to be fundamentally different from MMC (and thus, SD):

For example, SD cards will keep the data line low while they are busy, and it is high when they are not. Well, not Sony. Oh no! When the card is ready to continue communicating it will transmit bytes 0xAA or 0x55 on the line. Because of course that makes sense! But that is not all! There is a signal called Bus State, that toggles between phases of communication (approximately: command, handshake, data, and ack). Good so far? Here's a curveball: it toggles one bit BEFORE any given phase is over. So the last bit of any given phase is sent after it has toggled.

(From Dmitry.GR's reverse engineering efforts).

So, logic to handle state machines, to parse addresses and commands is necessary. That necessitates active components.

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