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This is a circuit which has parasitic capacitors:

enter image description here

--- MOSFET Transistors ---
    Name:          m1
    Model:       nmos-sh
    Id:          6.91e-05
    Vgs:         6.58e-01
    Vds:         1.03e+00
    Vbs:        -6.91e-02
    Vth:         4.20e-01
    Vdsat:       2.37e-01
    Gm:          5.82e-04
    Gds:         6.27e-06
    Gmb:         1.66e-04
    Cbd:         2.16e-14
    Cbs:         3.19e-14
    Cgsov:       3.58e-15
    Cgdov:       3.58e-15
    Cgbov:       0.00e+00
    Cgs:         7.11e-14
    Cgd:         0.00e+00
    Cgb:         0.00e+00

Version 4
SHEET 1 936 680
WIRE 224 160 80 160
WIRE 480 160 224 160
WIRE 80 176 80 160
WIRE 80 304 80 256
WIRE 144 304 80 304
WIRE 80 320 80 304
WIRE 80 320 64 320
WIRE 80 352 80 320
WIRE 144 400 80 400
WIRE 640 400 640 352
WIRE 800 400 800 352
WIRE -160 432 -208 432
WIRE -128 432 -160 432
WIRE -16 432 -16 320
WIRE -16 432 -48 432
WIRE 32 432 -16 432
WIRE 480 432 480 160
WIRE 80 464 80 448
WIRE 96 464 80 464
WIRE 80 480 80 464
WIRE -208 624 -208 512
WIRE 80 624 80 560
WIRE 80 624 -208 624
WIRE 144 624 144 400
WIRE 144 624 80 624
WIRE 480 624 480 512
WIRE 480 624 144 624
WIRE 640 624 640 480
WIRE 640 624 480 624
WIRE 800 624 800 480
WIRE 800 624 640 624
WIRE -208 640 -208 624
FLAG -208 640 0
FLAG 224 160 VDD
FLAG -16 432 VG
FLAG 144 304 VO
IOPIN 144 304 Out
FLAG 640 352 Vicm
FLAG 800 352 Vid
FLAG -160 432 VIN
FLAG 96 464 VS
IOPIN 96 464 Out
SYMBOL nmos4 32 352 R0
WINDOW 3 56 60 Left 2
SYMATTR Value NMOS-SH
SYMATTR InstName M1
SYMATTR Value2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u
SYMBOL voltage 480 416 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1.2
SYMBOL voltage 640 384 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vicm
SYMATTR Value 0.69
SYMBOL voltage 800 384 R0
WINDOW 3 24 152 Left 2
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value 0
SYMATTR Value2 AC 1
SYMATTR InstName Vid
SYMBOL bv -208 416 R0
WINDOW 0 -60 23 Left 2
SYMATTR InstName VIN1
SYMATTR Value V=V(Vicm)+V(Vid)
SYMBOL res 80 304 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rf1
SYMATTR Value 10k
SYMBOL res 64 160 R0
SYMATTR InstName RD
SYMATTR Value 1k
SYMBOL res -32 416 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RG
SYMATTR Value 1k
SYMBOL res 64 464 R0
SYMATTR InstName RS
SYMATTR Value 1k
TEXT -80 -8 Left 2 !.MODEL PMOS-SH pmos(kp=45u,vto=-0.42, lambda = {0.1/1}, gamma = 0.5, phi = 0.7\n+TOX=4.0n CGSO=0.28n CGBO=0 CGDO=0.28n CJ=1.38m CJSW=1.44n)
TEXT -80 48 Left 2 !.MODEL NMOS-SH nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7\n+TOX=4.0n CGSO=0.29n CGBO=0 CGDO=0.29n CJ=3.65m CJSW=0.79n)
TEXT -48 -40 Left 2 ;M1:  l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u
TEXT -240 192 Left 2 !.op\n.ac oct 10 100MEG 100G
TEXT -240 168 Left 2 !;tf V(VO) Vid
TEXT -240 144 Left 2 !;dc VDD 0 1.8 0.01

AC frequency analysis:

enter image description here

enter image description here

I tried to build an equivalent circuit in SPICE with external capacitors.

enter image description here

Version 4
SHEET 1 880 680
WIRE -64 -64 -208 -64
WIRE 192 -64 -64 -64
WIRE -208 -48 -208 -64
WIRE -208 80 -208 32
WIRE -208 80 -352 80
WIRE -144 80 -208 80
WIRE -352 96 -352 80
WIRE -208 96 -208 80
WIRE -208 96 -224 96
WIRE -208 112 -208 96
WIRE -144 112 -208 112
WIRE -208 128 -208 112
WIRE -144 176 -208 176
WIRE -80 176 -144 176
WIRE 352 176 352 128
WIRE 512 176 512 128
WIRE -80 192 -80 176
WIRE -448 208 -496 208
WIRE -352 208 -352 160
WIRE -352 208 -368 208
WIRE -304 208 -304 96
WIRE -304 208 -352 208
WIRE -256 208 -304 208
WIRE 192 208 192 -64
WIRE -304 256 -304 208
WIRE -208 256 -208 224
WIRE -208 256 -240 256
WIRE -112 256 -208 256
WIRE -80 256 -112 256
WIRE -208 288 -208 256
WIRE -112 288 -112 256
WIRE -496 400 -496 288
WIRE -208 400 -208 368
WIRE -208 400 -496 400
WIRE -144 400 -144 176
WIRE -144 400 -208 400
WIRE 192 400 192 288
WIRE 192 400 -144 400
WIRE 352 400 352 256
WIRE 352 400 192 400
WIRE 512 400 512 256
WIRE 512 400 352 400
WIRE -496 416 -496 400
FLAG -496 416 0
FLAG -64 -64 VDD
FLAG -304 208 VG
FLAG -144 80 VO
IOPIN -144 80 Out
FLAG 352 128 Vicm
FLAG 512 128 Vid
FLAG -496 208 VIN
FLAG -112 288 VS
IOPIN -112 288 Out
SYMBOL nmos4 -256 128 R0
WINDOW 3 56 60 Left 2
SYMATTR Value NMOS-SH
SYMATTR InstName M1
SYMATTR Value2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u
SYMBOL voltage 192 192 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1.2
SYMBOL voltage 352 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vicm
SYMATTR Value 0.69
SYMBOL voltage 512 160 R0
WINDOW 3 24 152 Left 2
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value 0
SYMATTR Value2 AC 1
SYMATTR InstName Vid
SYMBOL bv -496 192 R0
WINDOW 0 -91 59 Left 2
WINDOW 3 -132 101 Left 2
SYMATTR InstName VIN1
SYMATTR Value V=V(Vicm)+V(Vid)
SYMBOL res -208 80 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rf
SYMATTR Value 10k
SYMBOL res -224 -64 R0
SYMATTR InstName RD
SYMATTR Value 1k
SYMBOL res -352 192 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RG
SYMATTR Value 1k
SYMBOL res -224 272 R0
SYMATTR InstName RS
SYMATTR Value 1k
SYMBOL cap -240 240 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName Cgs
SYMATTR Value 74.68e-15
SYMBOL cap -160 112 R0
WINDOW 0 -30 12 Left 2
WINDOW 3 38 32 Left 2
SYMATTR InstName Cbd
SYMATTR Value 2.16e-14
SYMBOL cap -368 96 R0
WINDOW 0 -31 6 Left 2
WINDOW 3 -36 53 Left 2
SYMATTR InstName Cgd
SYMATTR Value 3.58e-15
SYMBOL cap -96 192 R0
SYMATTR InstName Cbs
SYMATTR Value 3.19e-14
TEXT -528 -32 Left 2 !.op\n.ac oct 10 100MEG 100G
TEXT -528 -56 Left 2 !;tf V(VO) Vid
TEXT -528 -80 Left 2 !;dc VDD 0 1.8 0.01
TEXT -384 -184 Left 2 !.MODEL PMOS-SH pmos(kp=45u,vto=-0.42, lambda = {0.14/1}, gamma = 0.5, phi = 0.7)
TEXT -384 -152 Left 2 !.MODEL NMOS-SH nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7)
TEXT -352 -216 Left 2 ;M1:  l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u

AC frequency analysis:

enter image description here

enter image description here

Why do this two circuits differ?

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24
  • 2
    \$\begingroup\$ Did you include sidewall capacitance and overlap capacitance in your equivalent model? Even if you did, I think they would never match completely. \$\endgroup\$
    – internet
    Commented Feb 17 at 16:09
  • 1
    \$\begingroup\$ I don't see large differences here, it seems they're pretty much the same. It'd be more useful if you overlay them, perhaps by exporting the data points and plotting on excel. \$\endgroup\$
    – Designalog
    Commented Feb 17 at 16:13
  • 2
    \$\begingroup\$ @kile Because your model is not the same as the model in LTspice. It's not that simple; you can check the help section M.MOSFETs on LTspice and also the BSIM model if you want to make it match exactly. I'm not interested in this. \$\endgroup\$
    – internet
    Commented Feb 18 at 15:09
  • 1
    \$\begingroup\$ @internet Since I already did this a couple days ago, I'll save everyone the trouble and just post a screenshot. i.sstatic.net/ZDJ5I.png \$\endgroup\$
    – Ste Kulov
    Commented Feb 24 at 8:53
  • 1
    \$\begingroup\$ Also, here is the SPICE small signal model. As long as Rd and Rs are zero (and they are), then the externally connected capacitors should match the topology. I'm convinced at this point that the only way to sort this out is to look at the source code and reverse engineer what's going on, which is impossible. You can also email [email protected] and ask them why the discrepancy exists. I also ran the same netlist in ngspice and the plots match exactly. i.sstatic.net/w23Cq.png \$\endgroup\$
    – Ste Kulov
    Commented Feb 24 at 9:11

2 Answers 2

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+50
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First, to make things easier, I reconstructed your LTspice schematic such that both versions you are trying to compare are within the same simulation. That way you can probe both outputs at the same time and compare the results more easily. I've included the text of my .asc file below if you want to run it yourself.

NOTE: Be careful when copying large blocks of schematic over like this. You have to be aware that even though reference designators will be changed on the copies of components, node labels WILL NOT. So you have to edit the node labels on the copy if you don't want those nodes to be shorted together. enter image description here

Version 4
SHEET 1 1076 1044
WIRE -224 16 -368 16
WIRE 32 16 -224 16
WIRE 1008 16 864 16
WIRE -368 32 -368 16
WIRE 864 32 864 16
WIRE 864 128 864 112
WIRE 864 128 720 128
WIRE 864 144 864 128
WIRE 928 144 864 144
WIRE -368 160 -368 112
WIRE -304 160 -368 160
WIRE -368 176 -368 160
WIRE -368 176 -384 176
WIRE 720 176 720 128
WIRE 864 176 864 144
WIRE 864 176 848 176
WIRE 912 176 864 176
WIRE -368 208 -368 176
WIRE 864 208 864 176
WIRE 912 208 912 176
WIRE 944 208 912 208
WIRE 1056 208 1008 208
WIRE -240 256 -368 256
WIRE 32 256 32 16
WIRE 192 256 192 208
WIRE 352 256 352 208
WIRE 1056 256 1056 208
WIRE 1056 256 864 256
WIRE -608 288 -656 288
WIRE -576 288 -608 288
WIRE -464 288 -464 176
WIRE -464 288 -496 288
WIRE -416 288 -464 288
WIRE 608 288 592 288
WIRE 720 288 720 240
WIRE 720 288 688 288
WIRE 768 288 768 176
WIRE 768 288 720 288
WIRE 816 288 768 288
WIRE -656 320 -656 288
WIRE -368 320 -368 304
WIRE -352 320 -368 320
WIRE -368 336 -368 320
WIRE 768 352 768 288
WIRE 864 352 864 304
WIRE 864 352 832 352
WIRE 896 352 864 352
WIRE 944 352 896 352
WIRE 1056 352 1056 256
WIRE 1056 352 1008 352
WIRE 864 400 864 352
WIRE 1056 400 1056 352
WIRE -656 432 -656 400
WIRE -368 432 -368 416
WIRE -368 432 -656 432
WIRE -240 432 -240 256
WIRE -240 432 -368 432
WIRE 32 432 32 336
WIRE 32 432 -240 432
WIRE 192 432 192 336
WIRE 192 432 32 432
WIRE 352 432 352 336
WIRE 352 432 192 432
WIRE 896 432 896 352
WIRE 928 432 896 432
WIRE -656 448 -656 432
WIRE 864 496 864 480
FLAG -656 448 0
FLAG -224 16 VDD
FLAG -464 288 VG1
FLAG -304 160 VO1
IOPIN -304 160 Out
FLAG 192 208 Vicm
FLAG 352 208 Vid
FLAG -608 288 VIN
FLAG -352 320 VS1
IOPIN -352 320 Out
FLAG 1008 16 VDD
FLAG 768 288 VG2
FLAG 928 144 VO2
IOPIN 928 144 Out
FLAG 592 288 VIN
FLAG 1056 400 0
FLAG 864 496 0
FLAG 928 432 VS2
IOPIN 928 432 Out
SYMBOL nmos4 -416 208 R0
WINDOW 3 56 60 Left 2
SYMATTR Value NMOS-SH1
SYMATTR InstName M1
SYMATTR Value2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u
SYMBOL voltage 32 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName VDD
SYMATTR Value 1.2
SYMBOL voltage 192 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName Vicm
SYMATTR Value 0.69
SYMBOL voltage 352 240 R0
WINDOW 3 24 152 Left 2
WINDOW 123 24 124 Left 2
WINDOW 39 0 0 Left 0
SYMATTR Value 0
SYMATTR Value2 AC 1
SYMATTR InstName Vid
SYMBOL bv -656 304 R0
WINDOW 0 -86 24 Left 2
SYMATTR InstName VIN1
SYMATTR Value V=V(Vicm)+V(Vid)
SYMBOL res -368 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rf1
SYMATTR Value 10k
SYMBOL res -384 16 R0
SYMATTR InstName RD1
SYMATTR Value 1k
SYMBOL res -480 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RG1
SYMATTR Value 1k
SYMBOL res -384 320 R0
SYMATTR InstName RS1
SYMATTR Value 1k
SYMBOL nmos4 816 208 R0
WINDOW 3 56 60 Left 2
SYMATTR Value NMOS-SH2
SYMATTR InstName M2
SYMATTR Value2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u
SYMBOL res 864 160 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName Rf2
SYMATTR Value 10k
SYMBOL res 848 16 R0
SYMATTR InstName RD2
SYMATTR Value 1k
SYMBOL res 880 496 R180
WINDOW 0 36 76 Left 2
WINDOW 3 36 40 Left 2
SYMATTR InstName RS2
SYMATTR Value 1k
SYMBOL cap 832 336 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName Cgs
SYMATTR Value 74.68e-15
SYMBOL cap 704 176 R0
WINDOW 0 -30 6 Left 2
WINDOW 3 -86 51 Left 2
SYMATTR InstName Cgd
SYMATTR Value 3.58e-15
SYMBOL res 704 272 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName RG2
SYMATTR Value 1k
SYMBOL cap 1008 192 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName Cbd
SYMATTR Value 2.16e-14
SYMBOL cap 1008 336 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName Cbs
SYMATTR Value 3.19e-14
TEXT -528 -152 Left 2 !.MODEL NMOS-SH1 nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7\n+TOX=4.0n CGSO=0.29n CGBO=0 CGDO=0.29n CJ=3.65m CJSW=0.79n)
TEXT -496 -184 Left 2 ;M1:  l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u
TEXT -688 48 Left 2 !.op\n.ac oct 10 100MEG 100G
TEXT -688 24 Left 2 !;tf V(VO) Vid
TEXT -688 0 Left 2 !;dc VDD 0 1.8 0.01
TEXT -528 -80 Left 2 !.MODEL NMOS-SH2 nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7)

I spent several hours looking for what could be the discrepancy between the plots and couldn't find it. I've included a photo below from page 213 of Semiconductor Device Modeling with SPICE, which shows the small signal model for the Level 1/2/3 SPICE MOSFET. As long as your RD (drain resistance) and RS (source resistance) parameters are zero (and they are), your external capacitor version should match the internal capacitor one.

enter image description here

Just for a sanity check I ran this simulation in various versions of LTspice which all produced the same results. I also ran it in ngspice and this is where it gets interesting. It produced results where the plots line up exactly on top of each other, which is what you would expect. Easiest way to run this is to put the below netlist into a file and drag/drop that file onto ngspice.exe.

enter image description here

* small signal MOSFET capacitance test
M1 VO1 VG1 VS1 0 NMOS-SH1 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u
VDD VDD 0 1.2
Vicm Vicm 0 0.69
Vid Vid 0 0 AC 1
B§VIN1 VIN 0 V=V(Vicm)+V(Vid)
Rf1 VO1 VG1 10k
RD1 VDD VO1 1k
RG1 VG1 VIN 1k
RS1 VS1 0 1k
M2 VO2 VG2 VS2 0 NMOS-SH2 l=1u w=12.35u ad=6.2p as=6.2p pd=13.4u ps=13.4u
Rf2 VO2 VG2 10k
RD2 VDD VO2 1k
RS2 0 VS2 1k
Cgs VS2 VG2 74.68e-15
Cgd VO2 VG2 3.58e-15
RG2 VG2 VIN 1k
Cbd 0 VO2 2.16e-14
Cbs 0 VS2 3.19e-14
.MODEL NMOS-SH1 nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7
+TOX=4.0n CGSO=0.29n CGBO=0 CGDO=0.29n CJ=3.65m CJSW=0.79n)
.ac oct 10 100MEG 100G
.MODEL NMOS-SH2 nmos(kp=180u,vto=0.4, lambda = {0.1/1}, gamma = 0.5, phi = 0.7)
.control
run
plot vdb(vo1), vdb(vo2)
.endc

There's definitely something going on here. I suggest emailing [email protected] and bringing this to their attention in case it's a bug of some kind. You can also try running it by the people over at the LTspice Google Groups. They know a lot of the inner workings of LTspice, short of knowing the actual source code.

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The LT spice mosfet model looks like this, so you don't have the eqivalent circuit when you put the capacitance on the outside of the model. For starters, the Rself (Rg) is on the other side of your cap.

This is the model that

enter image description here Source: Illustration of the MOSFET model for LTspice.

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  • \$\begingroup\$ Closer! But that's a custom model made by Swiss university EPFL (École Polytechnique Fédérale de Lausanne). Again, the two series resistances are zero in OP's circuit. \$\endgroup\$
    – Ste Kulov
    Commented Feb 27 at 0:12
  • \$\begingroup\$ Yeah, on lt wikis web page this is what the lt spice model is based off of, it doesn't matter, most models have RG and the capacitance is on the inside so almost any model will work to illustrate the differences \$\endgroup\$
    – Voltage Spike ♦
    Commented Feb 27 at 0:39

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