Your layout is exceptionally bad, particularly for such a high frequency (1.2MHz) SMPS chip.
The two loops (switch open and close) must be small area. The parts C4, C3 and L2 should be much closer to the chip and (in particular) the ground conductors should be very short. The capacitors should be connected to the ground plane very near the chip, not to some trace running away somewhere else on the board.
Always read and implement the suggestions such as "Layout Consideration" in the datasheet, and implement something very close to the recommended layout if one is provided (it is not in this case, but you might be able to find a similar chip where one is provided).
Here is a diagram showing the large loop areas in your layout, and the mystery part ‘?’ is outside this snippet. Your goal is to minimize the loop areas. Green loop is when the switch is ‘on’, blue when it is ‘off’. As well as affecting operation the loop areas affect EMI. The ‘?’ is the worst here, if the grounds were connected more directly with a jumper it might work, but would be unnecessarily noisy.
As well as making the loops small, it would also be better to have the two loops on top of each other as much as possible, so avoid the unnecessary branch shown to the right in green above and take that trace right from the D1 pad.
