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I'm seeking some advice about eye diagrams for analysing node behaviour on CAN for a prototype system.

I've been given this eye diagram, which is generated using Vector's .scope Canalyser tool and trying to understand what is going on here.

The eye diagram is generated using the tools "Window sweep" setting which, from what I understand, shows the timing of bit transitions relative to the expected speed of the CANBUS. So, in the eye diagram shown, the bus baud rate was 500k meaning that bit cells should be 2us.The pinky area is the bit mask, in which no bit transitions should encroach, especially the points at <= 75%, since this is where some CAN nodes will often sample the dominant or recessive state.

From the diagram, I could conclude that this particular node is running "up to 20% fast" relative to the expected baud rate which means that some of the trailing edges of bit transitions encroach upon the 75% sample point but I'm not 100% sure that this is a correct interpretation. The diagram relates to a particular node on the CANBUS; other nodes have transitions around the 0% and 100% points, which is what is expected.

It is also possible to view a frame in "VN" mode, where the bit cells are shown relative to the actual bus speed. Notionally, this seems more applicable, because it is my understanding that bit transitions are used to synchronise "clocks" on receiving nodes and this is why we have a stuff bit every so often to maintain clock synchronisation (or maybe it is just so that we can see that the bus is actually operational still?). In other words, it doesn't matter if a node has a slightly fast or slow clock just as long as it isn't wrong enough by more than 25% of a bit cell. Is this the correct interpretation?

If anyone has used this tool and has seen something like what is in the diagram, it'd be great if you could share what the root cause was.

Eye Diagram

Thanks in advance for any help.

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  • \$\begingroup\$ I'm not sure how to interpret this. What does Voltage = 2V even mean? No voltage of any relevant signal should ever be 2V. CANH should either be 2.5V or 3.5V. CANL should either be 2.5V or 1.5V. TX/RX should use logic levels (3.3V or 5V). So where does this come from? \$\endgroup\$
    – Lundin
    Commented Jan 12 at 7:39
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    \$\begingroup\$ As for the clocking, if it is as horrible as shown in the picture then the node is broken and must be redesigned. Very likely someone is using a highly unsuitable oscillator such as a built-in RC or ceramic resonator. You can use such for lower baudrates, but only if the manufacturer promises good accuracy close to 1%. \$\endgroup\$
    – Lundin
    Commented Jan 12 at 7:41
  • \$\begingroup\$ Thanks for the response. The 2V is the differential, which is pretty healthy I think; the line with the higher differential will be the ack pulse(s) to this frame. \$\endgroup\$
    – komandirskie
    Commented Jan 12 at 8:10
  • \$\begingroup\$ The timing is suspect, you are right. The device is using a ceramic resonator, so you have speculated correctly. The resonator has an absolute accuracy of 0.5% with a further temperature error of 0.15%, which I think is across the full temperature range. When you say "lower baudrates", what is this range? Would you classify 500k as a lower baud? I think the CAN standard specifies that the bit timing should be within 1.58%, which seems quite strict, but this is appears to be way outside of that. \$\endgroup\$
    – komandirskie
    Commented Jan 12 at 8:14
  • \$\begingroup\$ The standard makes the recommendation that baudrates of 250kbps or higher should use external quartz. You should keep it below 1.58% indeed, as bare minimum. I'd recommend closer to 1%. The reason for this is the detailed sample point setup used by the CAN controller. As for your timing issue, perhaps it is derived from the supply voltage? I'd peek at it with a scope, go down to mV range and AC, see if there's some misbehaving switch regulator or such. \$\endgroup\$
    – Lundin
    Commented Jan 12 at 9:08

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