How do P-type transistors conduct current?

Question

Going through a Introduction to Computing Systems by Yale N. Patt and Sanjay J. Patel and currently reading a chapter on MOS transistors. From what I understand, N-type transistors "close" a circuit when supplied with current and break it if absent. P-type transistors act in the opposite way. When supplied with current then it closes the circuit and breaks if present.

Now according to the textbook regarding the image below, "...if both A and B are supplied with 0 volts, the two P-type transistors conduct, and the output C is connected to 1.2 volts."

What I don't understand is where the 1.2 volts is coming from if input A and B are supplied with 0 volts? Based on the quote, I would assume that the power supply is coming from A and B but the only alternative I could think is that it is coming from the area indicated in red and that A and B are sort of like a light switch dictating the behaviour of the transistors

Answer 1

MOSFETs are controlled by their gate-to-source voltage, called Vgs. No current flows through the 'input' (gate). Rather, current flows through the other two terminals, called source and drain.

In typical CMOS logic, the n-FET sources is tied to GND, while the p-FET sources are tied to the supply (often called Vdd or Vcc).

Where does the logic-high voltage come from? Vdd is the logic voltage, which could be 5V, 3.3V, or some lower voltage such as 1.2V as mentioned in your example. Again, in your example, this logic-high power supply is connected to the top p-FET, as shown by your red arrow.

How do you get a logic high? When both p-FETs are on, the output is connected to power supply through both FETs in series.

On the low side, GND, or logic low, is supplied through the n-FETs. When either FET is on, the output is connected to GND.

Now, back to that gate-to-source voltage and what it does to the FETs:

• n-FET is 'on' when gate-source (Vgs) is positive, or logic '1'
• p-FET is 'on' when gate-source (Vgs) is negative, or logic '0'

If you work out the diagram and how the FETs behave, you can see 4 cases:

• A, B = 0, 0 => both p-FETs are 'on', n-FETs are off => output is HIGH
• A, B = 0, 1 => one p-FET is 'on', one n-FET is on => output is LOW
• A, B = 1, 0 => other p-FET is 'on', other n-FET is on => output is LOW
• A, B = 1, 1 => both p-FETs are 'off', both n-FETs are on => output is LOW

So what you have is a NOR gate. Try one out (simulate it here):

Answer 2

You first need to understand the distinction between BJTs and FETs; your textbook appears to be talking about FETs. Then, you need to understand the difference between enhancement mode and depletion mode FETs; your textbook appears to be talking about enhancement mode FETs. Then, you can talk about the differences between N-channel (or N-type) FETs and P-channel (or P-type) FETs.

N-channel enhancement mode FETs allow current to flow from drain to source when the gate terminal is at a higher voltage than the source terminal. P-channel enhancement mode FETs allow current to flow from source to drain when the gate terminal is at a lower voltage than the source terminal.