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The following is my schematic for active current mirror:

enter image description here

This is a SPICE simulation for my old question:

The following is the \$V_{out}\$ plot.

enter image description here

What's wrong with my \$V_{out}\$?

The asc file is provide here:

* G:\LTspice\Active_current_mirror_Amplifier.asc
I1 N007 0 100µ
V1 N001 0 5
Vin+ N004 0 SINE(0 10m 1Meg)
Vin- N006 0 SINE(0 -10m 1Meg) AC 1
C2 N003 Vout 10µ
M1 N001 N005 N007 0 NMOS l=1u w=176u
M2 N003 N005 N007 0 NMOS l=1u w=176u
M3 N001 N002 N003 N001 PMOS l=10u w=10u
M4 N001 N002 N002 N001 PMOS l=10u w=10u
I2 N002 0 50µ
R1 N001 N005 8Meg
R2 N005 0 2Meg
C1 N005 N004 10µ
C3 N006 N005 10µ
.model NMOS NMOS
.model PMOS PMOS
.lib C:\Users\jackh\Documents\LTspiceXVII\lib\cmp\standard.mos
.tran 0 1000u 990u 10m
.MODEL nmos nmos(kp=200u,vto=0.4, lambda = 0.1)
.MODEL pmos pmos(kp=200u,vto=-0.4, lambda =0.05)
;.op
;.ac lin 1000 1 1Meg
.meas Vo pp V(vout);
.meas Vi pp V(n004) - V(n005);
.meas Av param Vo/Vi
.backanno
.end
\$\endgroup\$
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  • \$\begingroup\$ Try real P and NMOS models with instead of the default ones. Try ramping up the current sources. \$\endgroup\$
    – winny
    Commented Dec 24, 2023 at 20:12
  • \$\begingroup\$ @winny I have tried ramping up the current source. But it's in vain \$\endgroup\$
    – kile
    Commented Dec 24, 2023 at 20:16
  • \$\begingroup\$ @C__ I doubt spice will accept \$\mu\$. \$\endgroup\$
    – kile
    Commented Dec 24, 2023 at 20:21
  • \$\begingroup\$ I'm struggling why you think this is an issue. I think it would be obvious to say that the output voltage is seeing a very small difference in voltage amplitude because there's probably cyclical capacitive voltage activity. Having an output margin of roughly +/- 0.13uV seems like an insignificant issue. So my question to you is: why are you concerned about Vo? If your goal was to create a differential op amp, then I'd say you created a rather balanced device. \$\endgroup\$
    – Colin
    Commented Dec 24, 2023 at 20:29
  • \$\begingroup\$ @C__ The book of razavi Design of Analog CMOS Integrated Circuits electrovolt.ir/wp-content/uploads/2014/08/…, page 147 give me this circuit. See fig 5.23 b \$\endgroup\$
    – kile
    Commented Dec 24, 2023 at 20:35

1 Answer 1

Reset to default
5
\$\begingroup\$

You have a wire shorting the inputs from the positive and negative sources in your circuit:

enter image description here

Since both sources Vin+ and Vin- are driving the circuit through identical 10 uF capacitors, the voltage signal at the gate node (the node connected to the gates of M1 and M2) is going to have essentially 0 amplitude, and therefore the sources are not going to affect the circuit at all. So it's no surprise there's no response at Vout.

\$\endgroup\$
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  • \$\begingroup\$ Thank you. It works now. Do you mean \$V_{g1} = V_{g2}\$ even in AC analysis? \$\endgroup\$
    – kile
    Commented Dec 24, 2023 at 21:20
  • 1
    \$\begingroup\$ Yes, in SPICE a short circuit forces all connected terminals to exactly the same voltage in any analysis at any frequency. \$\endgroup\$
    – The Photon
    Commented Dec 24, 2023 at 21:36
  • \$\begingroup\$ .... a short circuit does that in real life 😀 Spice is just simulating that \$\endgroup\$
    – Reversed Engineer
    Commented Dec 25, 2023 at 11:30
  • \$\begingroup\$ @ReversedEngineer, real "short circuits" have inductance and resistance. At some high frequency or high current there is a detectable difference in voltage between the two ends. SPICE short circuits are a mathematical assertion that two terminals are connected to the identical voltage (and only one variable exists in the nodal equations to represent that voltage). \$\endgroup\$
    – The Photon
    Commented Dec 25, 2023 at 17:40
  • \$\begingroup\$ @ThePhoton Sure, you're absolutely right! I actually implied that in my original comment, then deleted and recreated the comment to simplify it. Didn't seem to be relevant to the issue in question here. \$\endgroup\$
    – Reversed Engineer
    Commented Dec 26, 2023 at 9:04

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