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I am trying to design a double LC output filter on a buck topology.

I want to set the bandwidth of my converter to be at 20 kHz. The swithing frequency would be equal to 250 kHz. The first resonnance of the double LC output filter will be around 2 kHz and the second resonnance would be equal to 60 kHz. In this way, as mentionned in this article, The second filter resonance will be beyond the control loop crossover to avoid stability problems, but at a low enough frequency to attenuate both the switching frequency ripple and the high frequency noise.

The output capacitor of the "right filter" will be equal to 3 mF, I cannot change this value. The inductor of the "right filter" will be equal to 1 uH. I cannot change this value either...

Then with all the data mentionned and according to the previous article, it means that I need to have a first capacitor of the left "filter" equal to 7 uF and a first inductor equal to 1.3 uH of the left filter.

In summary here is the circuit:

enter image description here

In simulation (SIMPLIS) the buck is working with a type 2 compensation and I achieve a good phase margin and a good gain margin. But in the article mentionned, it is said the following design rules:

enter image description here

I completely do not respect the two yellow lines. But the buck is working. Do you think that it could be problematic to do not respect these "Design Rules"? I could increase the first inductor of the left filter to 10 uF, but it will affect the transient response of my converter. It will reduce the first resonnance frequency but it seems to be not a problem as my bandwidth is equal to 20 kHz. I tried to see the effect and effectively it affects the transient response for exactly the same parameters (I adjust the compensator to keep the same bandwidth) and the compensator cannot be faster as the inductor is limiting the speed of the converter as the slope of the current is limited. So It will be better to have a low inductor for fast transient. I know that it increased the ripple to have a lower inductance and so it means higher RMS current.

To sum it, the question is: If I do not respect the design rules of the article, what could be the problem? I.e having a low inductor equal to 1.3 uH and 7 uF on the first LC filter instead of 10 uF (or more) (10 times the right inductor) and 100 uF (or more) (2000 uF divided by 20).

Thank you very much.

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  • \$\begingroup\$ When you talk about the first resonance etc. can you be specific which LC you are referring to? It seems to me that first does not equal left etc.. \$\endgroup\$
    – Andy aka
    Commented Dec 2, 2023 at 13:44
  • \$\begingroup\$ Why are the values fixed as you claim? Start at the beginning, what are you designing for and why does it stipulate certain values? Then build from there. The referenced article might not be applicable to your situation. There also might not be a solution at all, if the values are fixed as you seem to suggest, in which case push-back is required. Is the converter design an open variable, or stipulated as well? \$\endgroup\$
    – Tim Williams
    Commented Dec 2, 2023 at 14:08
  • \$\begingroup\$ Hi, Thank you for your comment. I changed first by left, if I correclty understand what you wanted to mean. \$\endgroup\$
    – Jess
    Commented Dec 2, 2023 at 14:40
  • \$\begingroup\$ Thank you for your comment. This the capacitor and inductor of the "right filter" on the load side of an already existing board. The buck is an open variable. This is a general question about double LC stage filter on a buck topology. Or simply why the design rules suggest to have a right inductor equal to 10% of the left inductor ? Same question for the second filter. \$\endgroup\$
    – Jess
    Commented Dec 2, 2023 at 14:46
  • \$\begingroup\$ @Jess press CTRL-F and then enter "second" then, you'll see how many times you use the phrase and how many times you still need to correct it. \$\endgroup\$
    – Andy aka
    Commented Dec 2, 2023 at 16:36

1 Answer 1

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I think that if the gain and phase margin are good and you can achieve the required loop bandwidth you should be OK as far as the loop goes. However, be sure to test at different load conditions. If you're simulating, use an inductor model that incorporates saturation, or reduce the inductor value to the appropriate level for the load current you're testing with. If you're using ceramic caps be sure to account for DC bias, tolerance, AC excitation, temperature, aging, etc.

Now, you still have an LC filter OUTSIDE the control bandwidth of the loop, so there's potential there for ringing and overshoot/undershoot from load transients, hence rule #5.

So, test with your fastest load transients, and sweep the transient repetition frequency through the higher resonance to see what happens there.

If all those things look OK, I don't see any problem with violating the other rules, they're basically just design guidelines to make it easier to come up with a 2-stage filter. There are other ways to get there too.

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  • \$\begingroup\$ Thank you for your answer :) \$\endgroup\$
    – Jess
    Commented Dec 4, 2023 at 8:47

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