I recently learned that there is a phenomena called sampling gain effect in dc-dc converter and I am struggling to understand what this phenomena really is. Could someone enlighten me?
And I have seen a document where they are saying that using average current mode control (with a filter inside the feedback loop of the current) help to get rid of this effect. Is it true? How is it possible?
Let me try to give a simple answer to this question. Current-mode-controlled converters are made of two loops: an inner current loop and an outer loop which ensures voltage regulation. The error or control voltage \$v_c\$ does not set the duty ratio \$d\$ (as in voltage-mode control) but programs the inductor peak current \$i_L\$ and, indirectly, the duty ratio. It is the inner loop which does this job.
It is possible to model the current loop with the below illustration that I drawn for the article I published in How2Power some years ago:
This model is coming from Dr. Ray Ridley's work carried in 1990 and documented in his thesis available online.
In this model, you see a block \$H_e(s)\$ and it is describing the sampling operation: the inductor peak current is a discrete value updated cycle-by-cycle and that is the reason why Ridley used sampled-data analysis to model the loop. He did approximate \$H_e(s)\$ with a 2nd-order polynomial form featuring two right-half-plane zeroes. These two zeroes are located at half the switching frequency. It then becomes possible to visualize the control-to-inductor-peak-current transfer function which looks like this:
Unlike what people believe, there is no peaking in this inner current loop but its gain moves in relationship with the sense resistance, the various inductor slopes and the amount of injected compensation ramp via parameter \$m_c=1+\frac{S_e}{S_n}\$ with \$S_e\$ the external compensation ramp slope and \$S_n\$, the on-time slope. As the loop phase does not depend on the gain, at some point, if the gain is too strong (no compensation ramp and duty ratio approaching 50% in CCM), you have conditions for oscillations. Injecting an external ramp will force a crossover at a lower frequency, naturally building phase margin and stabilizing the current loop.
It is when the current loop is embedded into the outer voltage loop that the two RHP zeroes turn into double poles - the sub-harmonic poles - located at \$\frac{F_{SW}}{2}\$ and affected by a peaking you need to damp:
I have shown in the article how I built a digital modulator to measure the current loop transfer function in SIMPLIS and it perfectly confirms Ridley approach who also used a digital modulator on the bench for his experiments. As additional information, I looked at a way to differently model the current loop with a delay line here and the final theoretical results exactly match the power stage control-to-output transfer function obtained in SIMPLIS.
Pulse width modulation used in the control of power supplies essentially causes a phase delay in the loop, similar to the sampling delay in a pure digital system. When the inernal ramp voltage reaches the error amp voltage, switching occurs. This ends the pusle width. No other response can occur until the next period, thus it acts as a sampled system. The effective pole is phase only, and the effective phase delay is a function of frequency = 180*(F/2/Fsw). For example, at 1/5th your switching frequency Fsw, this delay would add 18deg phase shift additional to that caused by the analog components in your loop. The double pole due to peak current mode control has been explained by others here. It causes sub harmonic oscillations if it is not taken care of by slope compensation. However, the system still has the phase shift caused by the sampling delay.
